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2019

IEEE Transactions on VLSI 2019

Showing all 14 results

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A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS
~~₹15,000.00~~ ₹9,000.00
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A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories
~~₹18,000.00~~ ₹12,000.00
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A Low Complexity I/Q Imbalance Calibration Method for Quadrature Modulator
~~₹15,000.00~~ ₹10,000.00
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A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)
~~₹12,000.00~~ ₹6,000.00
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An Analog LO Harmonic Suppression Technique for SDR Receivers
~~₹20,000.00~~ ₹12,000.00
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CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency
~~₹10,000.00~~ ₹5,000.00
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Design of Reconfigurable Digital IF Filter with Low Complexity
~~₹18,000.00~~ ₹12,000.00
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Efficient Design for Fixed-Width Adder-Tree
~~₹16,000.00~~ ₹10,000.00
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Feed forward-Cutset-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator
~~₹16,000.00~~ ₹10,000.00
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Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping
~~₹15,000.00~~ ₹10,000.00
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Low-Power Approximate Unsigned Multipliers with Configurable Error Recovery
~~₹20,000.00~~ ₹12,000.00
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Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS
~~₹15,000.00~~ ₹10,000.00
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Multiloop Control for Fast Transient DC–DC Converter
~~₹16,000.00~~ ₹10,000.00
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Radiation-Hardened 14T SRAM Bit cell With Speed and Power Optimized for Space Application
~~₹10,000.00~~ ₹6,000.00
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A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS

A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories

A Low Complexity I/Q Imbalance Calibration Method for Quadrature Modulator

A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)

An Analog LO Harmonic Suppression Technique for SDR Receivers

CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency

Design of Reconfigurable Digital IF Filter with Low Complexity

Efficient Design for Fixed-Width Adder-Tree

Feed forward-Cutset-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator

Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping

Low-Power Approximate Unsigned Multipliers with Configurable Error Recovery

Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS

Multiloop Control for Fast Transient DC–DC Converter

Radiation-Hardened 14T SRAM Bit cell With Speed and Power Optimized for Space Application