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2019

IEEE Transactions on VLSI 2019

Showing 1–16 of 29 results

Sale!
A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS
~~₹15,000.00~~ ₹10,000.00
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A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage
~~₹12,000.00~~ ₹8,000.00
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A 7T Security Oriented SRAM Bitcell
~~₹12,000.00~~ ₹4,000.00
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A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories
~~₹20,000.00~~ ₹15,000.00
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A Low Complexity I/Q Imbalance Calibration Method for Quadrature Modulator
~~₹20,000.00~~ ₹15,000.00
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A Nanopower Biopotential Lowpass Filter Using Subthreshold Current-Reuse Biquads With Bulk Effect Self-Neutralization
~~₹10,000.00~~ ₹6,000.00
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A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)
~~₹15,000.00~~ ₹9,000.00
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A System of Two Coupled Oscillators With a Continuously Controllable Phase Shift
~~₹12,000.00~~ ₹6,000.00
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An Analog LO Harmonic Suppression Technique for SDR Receivers
~~₹20,000.00~~ ₹12,000.00
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Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate
~~₹10,000.00~~ ₹6,000.00
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Chaos-Based Bitwise Dynamical Pseudorandom Number Generator on FPGA
~~₹10,000.00~~ ₹6,000.00
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CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency
~~₹10,000.00~~ ₹5,000.00
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Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction
~~₹12,000.00~~ ₹6,000.00
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Design of Reconfigurable Digital IF Filter with Low Complexity
~~₹20,000.00~~ ₹15,000.00
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Efficient Design for Fixed-Width Adder-Tree
~~₹20,000.00~~ ₹12,000.00
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Energy-Quality Scalable Adders Based on Non-zeroing Bit Truncation
~~₹12,000.00~~ ₹6,000.00
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A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS

A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage

A 7T Security Oriented SRAM Bitcell

A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories

A Low Complexity I/Q Imbalance Calibration Method for Quadrature Modulator

A Nanopower Biopotential Lowpass Filter Using Subthreshold Current-Reuse Biquads With Bulk Effect Self-Neutralization

A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)

A System of Two Coupled Oscillators With a Continuously Controllable Phase Shift

An Analog LO Harmonic Suppression Technique for SDR Receivers

Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate

Chaos-Based Bitwise Dynamical Pseudorandom Number Generator on FPGA

CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency

Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction

Design of Reconfigurable Digital IF Filter with Low Complexity

Efficient Design for Fixed-Width Adder-Tree

Energy-Quality Scalable Adders Based on Non-zeroing Bit Truncation