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2019

IEEE Transactions on VLSI 2019

Showing all 35 results

Sale!
A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS
~~₹15,000.00~~ ₹10,000.00
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Sale!
A 13.4-MHz Relaxation Oscillator With Temperature Compensation
~~₹10,000.00~~ ₹6,000.00
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Sale!
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage
~~₹12,000.00~~ ₹8,000.00
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Sale!
A 7T Security Oriented SRAM Bitcell
~~₹12,000.00~~ ₹6,000.00
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Sale!
A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories
~~₹35,000.00~~ ₹15,000.00
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Sale!
A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace
~~₹35,000.00~~ ₹20,000.00
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Sale!
A Low Complexity I/Q Imbalance Calibration Method for Quadrature Modulator
~~₹20,000.00~~ ₹15,000.00
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Sale!
A Nanopower Biopotential Lowpass Filter Using Subthreshold Current-Reuse Biquads With Bulk Effect Self-Neutralization
~~₹10,000.00~~ ₹6,000.00
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Sale!
A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)
~~₹15,000.00~~ ₹9,000.00
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Sale!
A System of Two Coupled Oscillators With a Continuously Controllable Phase Shift
~~₹12,000.00~~ ₹6,000.00
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Sale!
A Two-Speed, Radix-4, Serial–Parallel Multiplier (Booth Multiplier )
~~₹15,000.00~~ ₹10,000.00
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Sale!
An Analog LO Harmonic Suppression Technique for SDR Receivers
~~₹20,000.00~~ ₹12,000.00
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Sale!
Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate
~~₹10,000.00~~ ₹6,000.00
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Sale!
Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches
~~₹15,000.00~~ ₹10,000.00
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Sale!
Chaos-Based Bitwise Dynamical Pseudorandom Number Generator on FPGA
~~₹10,000.00~~ ₹6,000.00
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Sale!
CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency
~~₹10,000.00~~ ₹5,000.00
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Sale!
Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction
~~₹12,000.00~~ ₹6,000.00
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Sale!
Design of Reconfigurable Digital IF Filter with Low Complexity
~~₹20,000.00~~ ₹15,000.00
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Sale!
Design of Sparse FIR Filters With Reduced Effective Length
~~₹12,000.00~~ ₹8,000.00
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Sale!
Efficient Design for Fixed-Width Adder-Tree
~~₹20,000.00~~ ₹12,000.00
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Sale!
Energy-Quality Scalable Adders Based on Non-zeroing Bit Truncation
~~₹12,000.00~~ ₹6,000.00
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Sale!
FPGA-Based System For Heart Rate Monitoring
~~₹45,000.00~~ ₹25,000.00
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Sale!
Highly Linear Low-Power Wireless RF Receiver for WSN
~~₹12,000.00~~ ₹8,000.00
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Sale!
Instantaneous Power Consuming Level Shifter for Improving Power Conversion Efficiency of Buck Converter
~~₹10,000.00~~ ₹7,000.00
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Sale!
Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping
~~₹18,000.00~~ ₹12,000.00
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Sale!
Low-Complexity 2-D Digital FIR Filters Using Polyphase Decomposition and Farrow Structure
~~₹18,000.00~~ ₹12,000.00
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Sale!
Low-Power Approximate Unsigned Multipliers with Configurable Error Recovery
~~₹22,000.00~~ ₹15,000.00
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Sale!
Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS
~~₹15,000.00~~ ₹10,000.00
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Sale!
Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow Phase-Noise Cellular Applications
~~₹10,000.00~~ ₹5,000.00
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Sale!
Multiloop Control for Fast Transient DC–DC Converter
~~₹18,000.00~~ ₹12,000.00
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Sale!
New Majority Gate Based Parallel BCD Adder Designs for Quantum-dot Cellular Automata
~~₹15,000.00~~ ₹10,000.00
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Sale!
Radiation-Hardened 14T SRAM Bit cell With Speed and Power Optimized for Space Application
~~₹12,000.00~~ ₹8,000.00
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Sale!
Static Delay Variations Modules For Ripple-Carry and Borrow Save Adders
~~₹18,000.00~~ ₹12,000.00
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Sale!
TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier
~~₹15,000.00~~ ₹12,000.00
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Sale!
World’s Fastest FFT Architectures: Breaking the Barrier of 100 GS/s
~~₹15,000.00~~ ₹8,000.00
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Cart

A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS

A 13.4-MHz Relaxation Oscillator With Temperature Compensation

A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage

A 7T Security Oriented SRAM Bitcell

A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories

A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace

A Low Complexity I/Q Imbalance Calibration Method for Quadrature Modulator

A Nanopower Biopotential Lowpass Filter Using Subthreshold Current-Reuse Biquads With Bulk Effect Self-Neutralization

A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)

A System of Two Coupled Oscillators With a Continuously Controllable Phase Shift

A Two-Speed, Radix-4, Serial–Parallel Multiplier (Booth Multiplier )

An Analog LO Harmonic Suppression Technique for SDR Receivers

Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate

Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches

Chaos-Based Bitwise Dynamical Pseudorandom Number Generator on FPGA

CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency

Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction

Design of Reconfigurable Digital IF Filter with Low Complexity

Design of Sparse FIR Filters With Reduced Effective Length

Efficient Design for Fixed-Width Adder-Tree

Energy-Quality Scalable Adders Based on Non-zeroing Bit Truncation

FPGA-Based System For Heart Rate Monitoring

Highly Linear Low-Power Wireless RF Receiver for WSN

Instantaneous Power Consuming Level Shifter for Improving Power Conversion Efficiency of Buck Converter

Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping

Low-Complexity 2-D Digital FIR Filters Using Polyphase Decomposition and Farrow Structure

Low-Power Approximate Unsigned Multipliers with Configurable Error Recovery

Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS

Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow Phase-Noise Cellular Applications

Multiloop Control for Fast Transient DC–DC Converter

New Majority Gate Based Parallel BCD Adder Designs for Quantum-dot Cellular Automata

Radiation-Hardened 14T SRAM Bit cell With Speed and Power Optimized for Space Application

Static Delay Variations Modules For Ripple-Carry and Borrow Save Adders

TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier

World’s Fastest FFT Architectures: Breaking the Barrier of 100 GS/s