Proposed Title :
FPGA Implementation of Forward Error Correction method of Hamming based SRAM Emulated TCAMs
Improvement of this Project:
Designed this 64×40 SRAM Emulated TCAM with FEC (Forward Error Correction) method of Hamming based error correction, to overcome the Parity method of Error correction code.
Designed 64×40, 512×40, 1024×40, 2048×40 with Block and Distributed Memory in Xilinx FPGA, and shown the performance of area, delay and power.
In a recent method of packet classification will have more priority in all network based applications, thus its required more memory processing to transfer and receive the data, for that the ternary content addressable memory will have used in this proposed work to reduced number of memory complications. In this recent method TCAM memory will have more complication to recover original data in receiver end, because in this error detection of TCAM memory only used with parity based error corrections only, it’s not more comfortable in all the packet classification it will create more packet loss and bit loss thus this proposed work will integrated forward error correction method of Hamming technique of single error correction will integrated and reduce the number of bit losses and packet losses in ternary content addressable memory. In this work will present parity based error correction of 64×40, 512×40, 1024×40, 2048×40 will evaluated in Xilinx FPGA with support of Block and distributed memory, and 64×40 TCAM will be integrated with forward error correction method. The parameters of area, delay and power will compared and proved the performance of all TCAM memory’s.
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Error Detection and Correction in SRAM Emulated TCAMs
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