MPEG has for long been the most preferred video compression scheme in modern video applications and devices. Using the MPEG-2/MPEG-4 standards, videos can be squeezed to very small sizes. MPEG uses both interframe and intraframe encoding for video compression. Intraframe encoding involves encoding the entire frame of data, while interframe encoding utilizes predictive and interpolative coding techniques as means of achieving compression. The interframe version exploits the high temporal redundancy between adjacent frames and only encodes the differences in information between the frames, thus resulting in greater compression ratios. In addition, motion compensated interpolative coding scales down the data further through the use of bidirectional prediction. In this case, the encoding takes place based upon the differences between the current frame and the previous and next frames in the video sequence.
MPEG encoding involves three kinds of frames:
- I-frames (intraframe encoded)
- P-frames (predictive encoded)
- B-frames (bidirectional encoded)
As evident from their names, an I-frame is encoded completely as it is without any data loss. An I-frame usually precedes each MPEG data stream. P-frames are constructed using the differences between the current frame and the immediately preceding I or P frame. B-frames are produced relative to the closest two I/P frames on either side of the current frame. The I, P, and B frames are further compressed when subjected to DCT, which helps to eliminate the existing interframe spatial redundancy as much as possible.
A significant portion of the interframe encoding is spent in calculating motion vectors (MVs) from the computed differences. Each non-encoded frame is divided into smaller macro blocks (MBs), typically 16 × 16 pixels. Each MV has an associated MB. The MVs actually contain information regarding the relative displacements of the MBs in the present frame in comparison with the reference. These are calculated by extracting the minimum value of sum of absolute differences (SADs) of an MB with respect to all the MBs of the reference frame. The resultant vectors are also encoded along with the frames. However, this is not sufficient to provide an accurate description of the actual frame. Hence, in addition to the MVs, a residual error is computed, which is then compressed using DCT. It has been proven that the ME and DCT blocks are the most computationally expensive components of an MPEG encoder , . The different steps involved in performing MPEG compression are shown in Fig. 1.
There are multiple ways of setting the hard threshold for the output PSNR, which determines whether the quality of a video is acceptable or not. For the sake of simplicity, it is assumed that either the absolute PSNR or the percentage change in PSNR serves as a faithful yardstick for evaluating the quality of videos outputted by the approximated MPEG encoder. In this regard, we define two metrics: 1) absolute error threshold (AET) and 2) relative error margin (REM) to demarcate between the acceptable and unacceptable videos. AET is defined as a fixed absolute PSNR value below which the video is termed to be unacceptable. REM is expressed as a certain percentage of the base PSNR value, which gives the maximum permissible degradation in output PSNR. Either of them can be utilized for judging the merit of a video. In the case AET is fixed at 25 (evaluated by a subjective assessment of the video qualities).
In the existing system to design the addition unit using ripple carry adder and carry look ahead adder design. In this to use the Dual Mode FA (DMFA) is used for low power consumption.For a reconfigurable CLA, DMCLB1 and DMCLB2 blocksare approximated in accordance with the DA. However,the DMPGB1 and DMPGB2 blocks are approximated onlywhen each and every DMCLB1, DMCLB2, DMPGB1,and DMPGB2 block, which belongs to the transitivefan-in cones of the concerned block, is approximated.Otherwise, the block is operated in the accurate mode.For example, any DMPGB block at the second level ofCLA can be made to operate in approximate mode, if andonly if, both of its constituent DMCLB1 and DMCLB2 blocksare operating in the approximate mode. Similar protocol isensued for the blocks residing at higher levels of the tree,where each DMPGB block can be approximated only whenboth of its constituent DMPGB1 and DMPGB2 blocks areapproximated. This architecture can be easily extrapolated toother similar type CLAs, such as Kogge–Stone, Brent–Kung,Manchester-carry chain, and so on.
- More Delay
- Less Power
Proposed System:In the existing system, the design of adder using RCA and CLA is take more delay. So the overall process of the MPEG encoder is affected by thus delays. The design needed to other adder with low delay. So we select the carry skip adder for this reason.A carry-skip adder is generally made up of a simple ripple carry-adder along with a special speed up carry chain is known as a skip chain. The distribution of ripple carry blocks is defined by this carry chain, which constitute the skip adder.The proposed scheme replaces each FA cell of theadders/subtractors with a Dual-Mode FA (DMFA) cell in which each FA cell can operate either in fully accurate or in some approximation mode depending on the state ofthe control signal APP. A logic high value of the APP signaldenotes that the DMFA is operating in the approximate mode.We term these adders/subtractors as RABs. By uses of DMFA the power consumption of the adder is reduced more compare the conventional adder.
Reconfigurable Adder/Subtractor Blocks:
Dynamic variation of the DA can be done when each of the adder/subtractor blocks is equipped with one or more of its approximate copies and it is able to switch between them as per requirement. This reconfigurable architecture can include any approximate version of the adders/subtractors.
As examples, we have chosen the two most naive methods presented, namely, truncation and approximation 5, for approximating the adder/subtractor blocks. The latter one can also be conceptualized as an enhanced version of truncation as it just relays the two 1-bit inputs, one as Sum and the other as Carry Out (Choice 2). In case A, B, and Cin are the 1-bit inputs to the full adder (FA), then the outputs are Sum=Band Cout=A. The resultant truth-table shows that the outputs are correct for more than half of all input combinations, thus proving to be a better approximation mode than truncation. The design of the DMFA is shown in figure 5.This design is implemented into the carry skip adder and analysis the performance of the adder. The details about the adder is given below.
- Optimized the power consumption
- Reduced the Delay