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High speed VLSI Design

Showing all 37 results

Sale!
A High Speed FPGA Implementation of an RSD Based ECC Processor
~~₹15,000.00~~ ₹10,000.00
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A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors
~~₹10,000.00~~ ₹6,000.00
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A Highly Efficient Conditional Feed through Pulsed Flip Flop for High Speed Applications
~~₹12,000.00~~ ₹10,000.00
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A Low Complexity I/Q Imbalance Calibration Method for Quadrature Modulator
~~₹20,000.00~~ ₹15,000.00
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A Multiuser Detection Algorithm in the Uplink SCFDMA System for Green Communication network
~~₹35,000.00~~ ₹25,000.00
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A Novel Quantum Dot Cellular Automata X bit × 32 bit SRAM
~~₹15,000.00~~ ₹8,000.00
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AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers
~~₹20,000.00~~ ₹15,000.00
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An Analog LO Harmonic Suppression Technique for SDR Receivers
~~₹20,000.00~~ ₹12,000.00
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An Efficient VLSI Architecture for Convolution Based DWT Using MAC
~~₹15,000.00~~ ₹8,000.00
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An Efficient VLSI Architecture of a Reconfigurable Pulse Shaping FIR Interpolation
~~₹15,000.00~~ ₹8,000.00
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Approximate Sum-of-Products Design Based on Distributed Arithmetic
~~₹16,000.00~~ ₹10,000.00
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Design and Development of OFDM Baseband Transceiver using VIRTEX 6 FPGA Family
~~₹15,000.00~~ ₹8,000.00
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Design and FPGA Implementation of Lattice Wave Digital Notch Filter with Minimal Transient Duration
~~₹16,000.00~~ ₹12,000.00
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Design of Reconfigurable Digital IF Filter with Low Complexity
~~₹20,000.00~~ ₹15,000.00
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Design of Sparse FIR Filters With Reduced Effective Length
~~₹12,000.00~~ ₹8,000.00
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FIR Filter Design based on FPGA
~~₹15,000.00~~ ₹10,000.00
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Floating Point Butterfly Architecture Based on Binary Signed Digit Representation
~~₹12,000.00~~ ₹8,000.00
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FPGA Implementation of Partially Parallel Encoder Architecture for Long Polar Code
~~₹12,000.00~~ ₹9,000.00
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FPGA-Based System For Heart Rate Monitoring
~~₹45,000.00~~ ₹25,000.00
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High Performance VLSI architecture for M-PSK modems
~~₹16,000.00~~ ₹10,000.00
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High Speed Area Efficient VLSI Architecture of Three Operand Binary Adder
~~₹20,000.00~~ ₹12,000.00
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High Speed Low Power and Highly Reliable Frequency Multiplier for DLL Based Clock Generator
~~₹12,000.00~~ ₹8,000.00
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Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping
~~₹18,000.00~~ ₹12,000.00
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Low Power Compressor Based MAC Architecture for DSP Applications
~~₹10,000.00~~ ₹6,000.00
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Low Power Split Radix FFT Processors Using Radix 2 Butterfly Units
~~₹10,000.00~~ ₹8,000.00
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Low Power System for Detection of Symptomatic Patterns in Audio Biological Signals
~~₹25,000.00~~ ₹14,000.00
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Low-Complexity 2-D Digital FIR Filters Using Polyphase Decomposition and Farrow Structure
~~₹18,000.00~~ ₹12,000.00
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Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption
~~₹16,000.00~~ ₹12,000.00
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Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
~~₹12,000.00~~ ₹9,000.00
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QPSK Modulator on FPGA
~~₹16,000.00~~ ₹10,000.00
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RF Power Gating A Low Power Technique for Adaptive Radios
~~₹15,000.00~~ ₹10,000.00
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RoBA Multiplier A Rounding Based Approximate Multiplier for High Speed yet Energy Efficient Digital Signal Processing
~~₹16,000.00~~ ₹12,000.00
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Sparse FIR Filter Design via Partial 1-Norm Optimization
~~₹15,000.00~~ ₹10,000.00
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Sale!
Speech Encryption Using Two Dimensional Chaotic Maps
~~₹30,000.00~~ ₹20,000.00
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Sale!
To develop and Implement Low Power, High Speed VLSI for Processing Signals using Multi rate Techniques Low Power Divider Using Vedic Mathematics
~~₹10,000.00~~ ₹4,500.00
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Sale!
VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability
~~₹25,000.00~~ ₹20,000.00
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Sale!
World’s Fastest FFT Architectures: Breaking the Barrier of 100 GS/s
~~₹15,000.00~~ ₹8,000.00
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A High Speed FPGA Implementation of an RSD Based ECC Processor

A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors

A Highly Efficient Conditional Feed through Pulsed Flip Flop for High Speed Applications

A Low Complexity I/Q Imbalance Calibration Method for Quadrature Modulator

A Multiuser Detection Algorithm in the Uplink SCFDMA System for Green Communication network

A Novel Quantum Dot Cellular Automata X bit × 32 bit SRAM

AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers

An Analog LO Harmonic Suppression Technique for SDR Receivers

An Efficient VLSI Architecture for Convolution Based DWT Using MAC

An Efficient VLSI Architecture of a Reconfigurable Pulse Shaping FIR Interpolation

Approximate Sum-of-Products Design Based on Distributed Arithmetic

Design and Development of OFDM Baseband Transceiver using VIRTEX 6 FPGA Family

Design and FPGA Implementation of Lattice Wave Digital Notch Filter with Minimal Transient Duration

Design of Reconfigurable Digital IF Filter with Low Complexity

Design of Sparse FIR Filters With Reduced Effective Length

FIR Filter Design based on FPGA

Floating Point Butterfly Architecture Based on Binary Signed Digit Representation

FPGA Implementation of Partially Parallel Encoder Architecture for Long Polar Code

FPGA-Based System For Heart Rate Monitoring

High Performance VLSI architecture for M-PSK modems

High Speed Area Efficient VLSI Architecture of Three Operand Binary Adder

High Speed Low Power and Highly Reliable Frequency Multiplier for DLL Based Clock Generator

Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping

Low Power Compressor Based MAC Architecture for DSP Applications

Low Power Split Radix FFT Processors Using Radix 2 Butterfly Units

Low Power System for Detection of Symptomatic Patterns in Audio Biological Signals

Low-Complexity 2-D Digital FIR Filters Using Polyphase Decomposition and Farrow Structure

Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption

Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication

QPSK Modulator on FPGA

RF Power Gating A Low Power Technique for Adaptive Radios

RoBA Multiplier A Rounding Based Approximate Multiplier for High Speed yet Energy Efficient Digital Signal Processing

Sparse FIR Filter Design via Partial 1-Norm Optimization

Speech Encryption Using Two Dimensional Chaotic Maps

To develop and Implement Low Power, High Speed VLSI for Processing Signals using Multi rate Techniques Low Power Divider Using Vedic Mathematics

VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability

World’s Fastest FFT Architectures: Breaking the Barrier of 100 GS/s