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High speed VLSI Design

Showing 1–16 of 29 results

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A High Speed FPGA Implementation of an RSD Based ECC Processor
~~₹15,000.00~~ ₹10,000.00
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A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors
~~₹10,000.00~~ ₹6,000.00
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A Low Complexity I/Q Imbalance Calibration Method for Quadrature Modulator
~~₹20,000.00~~ ₹15,000.00
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A Multiuser Detection Algorithm in the Uplink SCFDMA System for Green Communication network
~~₹35,000.00~~ ₹25,000.00
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A Novel Quantum Dot Cellular Automata X bit × 32 bit SRAM
~~₹15,000.00~~ ₹8,000.00
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An Analog LO Harmonic Suppression Technique for SDR Receivers
~~₹20,000.00~~ ₹12,000.00
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An Efficient VLSI Architecture for Convolution Based DWT Using MAC
~~₹15,000.00~~ ₹8,000.00
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An Efficient VLSI Architecture of a Reconfigurable Pulse Shaping FIR Interpolation
~~₹15,000.00~~ ₹8,000.00
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Approximate Sum-of-Products Design Based on Distributed Arithmetic
~~₹16,000.00~~ ₹10,000.00
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Design and Development of OFDM Baseband Transceiver using VIRTEX 6 FPGA Family
~~₹15,000.00~~ ₹8,000.00
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Design of Reconfigurable Digital IF Filter with Low Complexity
~~₹20,000.00~~ ₹15,000.00
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FIR Filter Design based on FPGA
~~₹15,000.00~~ ₹10,000.00
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Floating Point Butterfly Architecture Based on Binary Signed Digit Representation
~~₹12,000.00~~ ₹8,000.00
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FPGA Implementation of Partially Parallel Encoder Architecture for Long Polar Code
~~₹12,000.00~~ ₹9,000.00
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High Performance VLSI architecture for M-PSK modems
~~₹16,000.00~~ ₹10,000.00
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High Speed Low Power and Highly Reliable Frequency Multiplier for DLL Based Clock Generator
~~₹12,000.00~~ ₹8,000.00
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A High Speed FPGA Implementation of an RSD Based ECC Processor

A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors

A Low Complexity I/Q Imbalance Calibration Method for Quadrature Modulator

A Multiuser Detection Algorithm in the Uplink SCFDMA System for Green Communication network

A Novel Quantum Dot Cellular Automata X bit × 32 bit SRAM

An Analog LO Harmonic Suppression Technique for SDR Receivers

An Efficient VLSI Architecture for Convolution Based DWT Using MAC

An Efficient VLSI Architecture of a Reconfigurable Pulse Shaping FIR Interpolation

Approximate Sum-of-Products Design Based on Distributed Arithmetic

Design and Development of OFDM Baseband Transceiver using VIRTEX 6 FPGA Family

Design of Reconfigurable Digital IF Filter with Low Complexity

FIR Filter Design based on FPGA

Floating Point Butterfly Architecture Based on Binary Signed Digit Representation

FPGA Implementation of Partially Parallel Encoder Architecture for Long Polar Code

High Performance VLSI architecture for M-PSK modems

High Speed Low Power and Highly Reliable Frequency Multiplier for DLL Based Clock Generator