Proposed Title :
Modified High Definition SPWM Generation on FPGAs with Harmonic
Mitigation for Voltage Source Inverter Applications
Improvement of this Project:
To design and modified the Hardware architecture of High Definition SPWM Generation With Harmonic Mitigation System due to performance utilization and hence proved with area, delay and power comparisons.
· To design the sampling frequency at 4 MHz and switching frequency at 20 KHz range.
· To design the proposed hardware architecture at Vertex 7 FPGA, regarding to improve the performance range of high speed utilization.
Switching using high resolution sinusoidal pulse width modulation (SPWM) is advantageous in order to produce limited capability and fine sinusoidal output of dc-ac converters. This paper proposes a unique FPGA based high definition SPWM ( HD-SPWM) architecture for integrating a lower frequency PWM train to a high frequency SPWM train in order to minimize inverter output with harmonics while attaining high resolution output. An optimized FPGA based two stage finite state machine (FSM) architecture is designed, where the initial stage decide pulse widths of a lower frequency PWM train based on the premeditate pulse width of the high frequency SPWM train, and the final stage integrates lower frequency PWM pulse width the high frequency SPWM pulse widths to generate updated high frequency SPWM pulse width, i.e HD-SPWM. Furthermore, a pre-formulation mathematical model for calculating duty cycle count value of pulse trains is constructed to allow the continuous modification of the HD modulation SPWM’s index (MI). The suggested generation has the advantages of harmonic mitigation, continuous fine adjustment of MI, quick processing time, and the demand of a small portion of a medium sized FPGA resulting in a favorable tradeoff between bigger designs and greater performance. Finally the proposed approach to design and modified the Hardware architecture of High Definition SPWM Generation With Harmonic Mitigation System due to performance utilization and hence proved with area, delay and power comparisons. To design the sampling frequency at 4 MHz and switching frequency at 20 KHz range. To design the proposed hardware architecture at Vertex 7 FPGA, regarding to improve the performance range of high speed utilization.
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FPGA Based High Definition SPWM Generation With Harmonic Mitigation Property for Voltage Source Inverter Applications
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