Proposed Title :
FPGA Implementation of Low-Cost and High Performance Montgomery Modular Multiplication with Adaptive Hold Logic based Error Correction
Improvement of this Project:
In proposed system we are check the output and correct the output if error occurs. In this system we are use the Adaptive Hold Logic
(AHL) is to detect and correct the error in the output.
To design the 32-Bit Montgomery Modular Multiplication and this Montgomery multiplication integrated with error correction using razor flip flop with support of adaptive hold logic method.
- Compared the existing 32-bit Montgomery Modular Multiplication with Proposed 32-bit Montgomery Modular Multiplication in terms of area, delay and power.
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LOW Cost High Performance VLSI Architecture for Montgomery Modular Multiplication
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