## Description

**Existing System:**

In existing system the SCS based Montgomery multiplier design having more hardware complexity and short critical path will be lessened. To overcome the weakness, we then modify the one-level CSA architecture to be able to perform one three-input carry-save addition or two serial two-input carry-save additions, so that the extra clock cycles for format conversion can be reduced by half. Finally, the condition and detection circuit, which are different with that of FCS-MMM42 multiplier, and also developed to pre-compute quotients and skip the unnecessary carry-save addition operations in the one-level configurable CSA (CCSA) architecture while keeping a short critical path delay. Therefore, the required clock cycles for completing one MM operation can be significantly reduced. As a result, the proposed Montgomery multiplier can obtain higher throughput and much smaller area-time product (ATP) than previous Montgomery multipliers.

**Disadvantages:**

- Short Critical path
- More hardware complexity
- More Power consumption
- More Cost

**Proposed System**

We are propose a new SCS-based Montgomery MM algorithm to reduce the critical path delay of Montgomery multiplier. In addition, the drawback of more clock cycles for completing one multiplication is also improved while maintaining the advantages of short critical path delay and low hardware complexity.

On the bases of critical path delay reduction, clock cycle number reduction, and quotient pre-computation reduction. A new SCS-based Montgomery MM algorithm using one-level Carry Skip Logic architecture is proposed to significantly reduce the required clock cycles for completing one MM.As shown in SCS-MM-New algorithm will be shown below,

**Carry skip adder**

A carry-skip adder is generally made up of a simple ripple carry-adder along with a special speed up carry chain is known as a skip chain. The distribution of ripple carry blocks is defined by this carry chain, which constitute the skip adder.

**Carry skip mechanism**

The summation of two digits which is of binary at phase i, where i not equal to zero (i ≠ 0), The input bit carry-in (Ci) will be dependent of the ripple carry adder, which in fact is the carry-out, Ci-1 of the previous phase. Therefore, it is clear that in order to compute the sum and the carry out, Ci+1, of phase i, one should know the carry-in (Ci) in advance. In some scenarios Ci+1can be computed without the actual knowledge of Ci.

The Boolean equations of a full adder is given as,

Pi = Ai xor Bi

Si = Pi xor Ci

Ci+1 = Ai Bi + Ci Pi

Where,

Pi => carry propagate of i^{th}phase

Si => Sum propagate of i^{th} phase

Ci+1 => Carry out of i^{th} Phase

Assuming that Ai= Bi, then propagate Pi equation would become zero. This will leaves the Ci+1 to depend only upon the input bits Ai and Bi, without the need of knowing the value of input Ci

Ai = Bi Pi = 0

If Ai = Bi = 0 Ci+1 = AiBi = 0

If Ai = Bi = 1Ci+1 = AiBi = 1

If the above given equation is true when the carry-out Ci+1 is one when Ai = Bi =1 or zero when Ai = Bi = 0.

The main intension of the carry bypass adder architecture is to providesthe blocks to be configured to shortens the lengthy life of a carry, which is the time required from its generation to the time required for the generation of next carry.

The delay of carry bypass adder is given as

t = t_{setup} + mt_{carry} + (n/m – 1) t_{carry} + t_{sum}

where,

n adder length

m length of the blocks

**Advantages:**

- Reduced Critical path
- Less Hardware Complexity
- Less Power Consumption
- High Performance