FPGA Implementation of Partially Parallel Encoder Architecture for Long Polar Code

Description

Proposed System: we propose a partially parallel structure to encode long polar codes efficiently. To clearly show the proposed approach and how to transform the architecture, a 4-parallel encoding architecture for the 16-bit polar code is exemplified in depth. The fully parallel encoding architecture is first transformed to a folded from and then the lifetime analysis and register allocation are applied to the folded architecture. Lastly, the proposed parallel architecture true for long polar code is described. Advantages: Less Hardware complexity More power consumption Support for long polar codes Software used:                                                            Modelsim Xilinx 14.2

Existing System:

Polar code is a new class of error correcting codes that provably achieves the capacity of the underlying channels. In addition concrete algorithms for constructing, encoding and decoding the code are all developed. Due to the channel capacity achieving property, the polar code is now considered as a major breakthrough in coding theory, and the applicability of the polar code is being investigated in many application including data storage devices. The property of efficient error correcting codes based upon the channel capacity, the code length should be at least 2²⁰ bits, and many literature works introduces polar codes ranging from 2¹⁰ to 2¹⁵to achieve good error-correcting performances in practice. In addition, the size of a message protected by an error-correcting code in storage systems in normally 4096 bytes. Although the polar code has been regarded as being associated with low complexity, such a long polar code suffers from severe hardware complexity and long latency,.

The polar code utilizes the channel polarization phenomenon that each channel approaches either a perfectly reliable or a completely noisy channel as the code length goes to infinity over a combined channel constructed with a set of N identical sub-channels. As the reliability of each sub-channel known a priori, K most reliable sub-channels are used to transmit information and the remaining sub-channels are set to predetermined values to construct a polar (N,K) code. The fully parallel encoder is intuitively designed based on the generator matrix, but implementing such an encoder becomes a significant burden when a long polar code is used to achieve a good error correcting performance. In Practical implementation, the memory size and the number of XOR gates increase as the code length increases.

Disadvantages:

1. More Hardware complexity
2. More Power dissipation
3. Not support for long polar codes

Proposed System: In this section, we propose a partially parallel structure to encode long polar codes efficiently. To clearly show the proposed approach and how to transform the architecture, a 4-parallel encoding architecture for the 16-bit polar code is exemplified in depth. The fully parallel encoding architecture is first transformed to a folded from and then the lifetime analysis and register allocation are applied to the folded architecture. Lastly, the proposed parallel architecture true for long polar code is described. In the proposed system of 4 parallel architecture of polar code to be re-modified and to implement 8-parallel architecture of polar code, and finally show the same power consumption, and the report of area, delay and logic sizes. Advantages

1. Less Hardware complexity
2. More power consumption
3. Support for long polar codes