THE dedicated short-range communication (DSRC) is a protocol for one- or two-way medium range communication especially for intelligent transportation systems. The DSRC can be briefly classified into two categories: automobile-to-automobile and automobile-to-roadside. In automobile-to-automobile, the DSRC enables the messages ending and broadcasting among automobiles for safety issues and public information announcement. The safeties issues include blind-spot, intersection warning, inter cars distance, and collision-alarm. The automobile-to-roadside focuses on the intelligent transportation service, such as electronic toll collection (ETC) system.
With ETC, the toll collecting is electrically accomplished with the contact less IC-card platform. Moreover, the ETC can be extended to the payment for parking-service, and gas-refueling. Thus, the DSRC system plays an important role in modern automobile industry. The system architecture of DSRC transceiver is shown in Fig. 1. The upper and bottom parts are dedicated for transmission and receiving, respectively. This transceiver is classified into three basic modules: microprocessor, baseband processing, and RF front-end. The microprocessor interprets instructions from media access control to schedule the tasks of baseband processing and RF front-end. The baseband processing is responsible for modulation, error correction, clock synchronization, and encoding. The RF front end transmits and receives the wireless signal through the antenna.
For each X, the FM0 code consists of two parts: one for former-half cycle of CLK, A, and the other one for later-half cycle of CLK, B. the coding principle of FM0 is listed as the following three rules.
- If X is the logic-0, the FM0 code must exhibit a transition between A and B.
- If X is the logic-1, no transition is allowed between A and B.
- The transition is allocated among each FM0 code no matter what the X is.
CLKA (t) + CLKB (t). (1)
The Manchester code is derived from
X ⊕CLK. (2)
The Manchester encoding is realized with a XOR operation for CLK and X. The clock always has a transition within one cycle, and so does the Manchester code no matter what the X is.
The hardware architectures of FM0 and Manchester encoders are shown in Fig. 2. The top part is the hardware architecture of FM0 encoder, and the bottom part is the hardware architecture of Manchester encoder. As listed in (1), the Manchester encoder is as simple as a XOR operation for X and CLK. Nevertheless, the FM0 encoding depends not only on the X but also on the previous-state of the FM0 code. The DFFA and DFFB store the state code of the FM0 code. The MUX−1 is to switch A (t) and B (t) through the selection of CLK signal.
- More Area and power dissipation
- Efficiency is low
The purpose of SOLS technique is to design a fully reused VLSI architecture for FM0 and Manchester encodings. The SOLS technique is classified into two parts: area-compact retiming and balance logic-operation sharing. Each part is individually described as follows. Finally, the performance evaluation of the SOLS technique is given.
The logic for A (t) and the logic for B (t) are the Boolean functions to derive A (t) and B (t), where the X is omitted for a concise representation. For FM0, the state code of each state is stored into DFFA and DFFB.
Thus, the FM0 encoding just requires a single 1-bit flip-flop to store the B (t−1).If the DFFA is directly removed, a non synchronization between A(t) and B(t)causes the logic fault of FM0 code. To avoid this logic-fault, the DFFB is relocated right after the MUX−1, as shown in Fig. 4(b), where the DFFB is assumed to be positive-edge triggered. At each cycle, the FM0 code, comprising A and B, is derived from the logic of A (t) and the logic of B (t), respectively. The FM0 code is alternatively switched between A (t) and B (t) through the MUX−1 by the control signal of the CLK. In Fig. 4(a), the Q of DFFB is directly updated from the logic of B (t) with 1-cycle latency. In Fig. 4(b), when the CLK is logic-0, the B (t) is passed through MUX−1totheDof DFFB. Then, the upcoming positive-edge of CLK updates it to the Q of DFFB. As shown in Fig. 8, the timing diagram for the Q of DFFB is consistent whether the DFFB is relocated or not.
Balance Logic-Operation Sharing:
This can be realized by the multiplexer, as shown in Fig. 5(a). It is quite similar to the Boolean function of FM0 encoding in (1). By comparing with (3) and (1), the FM0 and Manchester logics have a common point of the multiplexer like logic with the selection of CLK. As shown in Fig. 5(b), the concept of balance logic-operation sharing is to integrate the X into A (t) and X into B (t), respectively. The logic for A (t)/X is shown in Fig.6.The A (t) can be derived from an inverter of B (t −1), and X is obtained by an inverter of X. The logic for A (t)/X can share the same inverter, and then a multiplexer is placed before the inverter to switch the operands of B (t −1) and X. The Mode indicates either FM0 or Manchester encoding is adopted. The similar concept can be also applied to the logic for B (t)/X, as shown in Fig. 7(a).
Nevertheless, this architecture exhibits a drawback that the XOR is only dedicated for FM0 encoding, and is not shared with Manchester encoding. Therefore, the HUR of this architecture is certainly limited. The X can be also interpreted as the X⊕0, and thereby the XOR operation can be shared with Manchester and FM0 encodings. As a result, the logic for B (t)/X is shown in Fig. 7(b), where the multiplexer is responsible to switch the operands of B (t−1) and logic-0. This architecture shares the XOR for both B (t) and X, and thereby increases the HUR.
Furthermore, the multiplexer in Fig. 7(b) can be functionally integrated into the relocated DFFB from area-compact retiming technique, as shown in Fig. 7(c). The CLR is the clear signal to reset the content of DFFB to logic-0. The DFFB can be set to zero by activating CLR for Manchester encoding. When the FM0 code is adopted, the CLR is disabled, and the B (t−1) can be derived from DFFB. Hence, the multiplexer in Fig. 7(b) can be totally saved, and its function can be completely integrated into the relocated DFFB. The proposed VLSI architecture of FM0/Manchester encoding using SOLS technique is shown in Fig. 8.
Miller encoder and FM0 encoder combination :
Miller encoding is also known as delay encoding. It can be used for higher operating frequency and it is similar to Manchester encoding except that the transition occurs in the middle of an interval when the bit is 1. While using the Miller delay, noise interference can be reduced.
The block diagram has a d flip flop, t flip flop, NOT gate, and XOR gate. Where the input is A_in and CLK, then the output is a Miller output. For example, if the input is 0 and the clock, given the XOR operation has done that, is A_in CLK , therefore 0 plus a positive edge clock produces the output as 0. Given to d flip flop, the clock has inverted, and after that output is given to t flip flop it inputs as d flip flop output, which is 0. Then the TFF is toggle FF, which produces the Miller output as 1.
The four states available are 00, 01, 10, 11. There is also RST. Transition is obtained based on 1 and 0. In the initial state, reset is 1. Then the next state will be 00, and after this reset it will always be 0. When the input is 0, and the current state is 00, the next state is 10. If the input is 1, and the current state is 00, the next state is 01. If the input is 0, and the current state is 01, the next state is 10. And if the input is 1, and the current state is 01, the next state is 01. If the input is 0, and the current state is 10, the next state will be 11. If the input is 1, and the current state 10, the next state is 00. If the input is 0, and the current state is 11, the next state will be 01. And if the input is 1, and the current state is 11, the next state is 10.
- Fully reused VLSI architecture
- Eliminates the limitation on hardware utilization
- Xilinx ISE
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