## Description

**Existing System:**

Interleaving is a process that disperses the positions of the data bits before transmission so that the corrupted information can be recovered at the receiver by rearranging the data. An interleaver is a device that performs interleaving. A deinterleaver is always associated with every interleaver that restores the original input data sequence. Many papers in the literature have addressed the issue of designing interleaver in order to achieve low bit error rate. On the other hand, very few papers have addressed the efficient implementation issue of the interleavers.

**Disadvantages**:

- More Area and power dissipation
- Not Implemented on Image Processing

**Proposed System:**

Interleaving is the process of rearranging the ordering of data sequence before transmission. Block interleaver is a popular interleaver employed in digital data transmission. It is simple and easy to implement whereas the other types of interleavers offer complexity in implementing. A block interleaver is in the form of a row-column matrix of size R*C; where R is total number of rows and C is the total number of columns. To perform interleaving, the information is written to the R*C row-column matrix row wise and read back in column wise as shown in Figure 1. There are no inter-row or inter-column permutations used in this illustration, thus the interleaved sequence holds some systematic order. The block deinterleaver performs the inverse operation of the interleaver in which the information is written to the R*C row-column matrix column wise and read back in row wise.

**Interleavers and Deinterleavers**

Interleavers and Deinterleavers are designed and used in the context of characteristics of the errors that might occur when the message bits are transmitted through a noisy channel. To understand the functions of an interleaver/Deinterleaver, understanding of error characteristics is essential. Two types are errors concern communication system design engineer. They are burst error and random error

**Random Errors:**

Error locations are independent of each other. Error on one location will not affect the errors on other locations. Channels that introduce these types of errors are called channels without memory (since the channel has no knowledge of error locations since the error on location does not affect the error on another location).

**Burst Errors:**

Errors are depended on each other. For example, in channels with deep fading characteristics, errors often occur in bursts (affecting consecutive bits). That is, error in one location has a contagious effect on other bits. In general, these errors are considered to be dependent and such channels are considered to be channels with memory.

**Interleaver/Deinterleaver:**

One of the most popular ways to correct burst errors is to take a code that works well on random errors and interleave the bursts to “spread out” the errors so that they appear random to the decoder. There are two types of interleavers commonly in use today, block interleavers and convolutional interleavers.

The block interleaver is loaded row by row with L code words, each of length n bits. These L code words are then transmitted column by column until the interleaver is emptied. Then the interleaver is loaded again and the cycle repeats. At the receiver, the code words are deinterleaved before they are decoded. A burst of length L bits or less will cause no more than 1 bit error in any one codeword. The random error decoder is much more likely to correct this single error than the entire burst. The parameter L is called the interleaver degree, or interleaver depth. The interleaver depth is chosen based on worst case channel conditions. It must be large enough so that the interleaved code can handle the longest error bursts expected on the channel. The main drawback of block interleavers is the delay introduced with each row-by-row fill of the interleaver.

A block interleaver is in the form of a row-column matrix of size R*C; where R is total number of rows and C is the total number of columns. To perform interleaving, the information is written to the R*C row-column matrix row wise and read back in column wise as shown in Figure 4. There are no inter-row or inter-column permutations used in this illustration, thus the interleaved sequence holds some systematic order. The block deinterleaver performs the inverse operation of the interleaver in which the information is written to the R*C row-column matrix column wise and read back in row wise.

**BPSK Modulation:**

In digital modulation techniques a set of basic functions are chosen for a particular modulation scheme. Generally the basic functions are orthogonal to each other. Basis functions can be derived using ‘Gram Schmidt orthogonalization‘ procedure. Once the basis function are chosen, any vector in the signal space can be represented as a linear combination of the basic functions.

In Binary Phase Shift Keying (BPSK) only one sinusoid is taken as basis function modulation. Modulation is achieved by varying the phase of the basis function depending on the message bits. The following equation outlines BPSK modulation technique.

S0 (t) =A.cos (ωt) →represents ‘0’

S1 (t) =A.cos (ωt+π) →represents ‘1’

The constellation diagram of BPSK will show the constellation points lying entirely on the x axis. It has no projection on the y axis. This means that the BPSK modulated signal will have an in-phase component (I) but no quadrature component (Q). This is because it has only one basis function.

A BPSK modulator can be implemented by NRZ coding the message bits (1 represented by +ve voltage and 0 represented by -ve voltage) and multiplying the output by a reference oscillator running at carrier frequency ω.

**BPSK Demodulation:**

For BPSK demodulator, a coherent demodulator is taken as an example. In coherent detection technique the knowledge of the carrier frequency and phase must be known to the receiver. This can be achieved by using a Costas loop or a PLL (phase lock loop) at the receiver. A PLL essentially locks to the incoming carrier frequency and tracks the variations in frequency and phase. For the following simulation, neither a PLL nor a Costas loop is used but instead we simple use the output of the PLL or Costas loop. For demonstration purposes we simply assume that the carrier phase recovery is done and simply use the generated reference frequency at the receiver (cos (ωt)).

In the demodulator the received signal is multiplied by a reference frequency generator (assuming the PLL/Costas loop be present). The multiplied output is integrated over one bit period using an integrator. A threshold detector makes a decision on each integrated bit based on a threshold. Since an NRZ signaling format is used with equal amplitudes in positive and negative direction, the threshold for this case would be ‘0’.

**Advantages:**

- Resource utilization
- Power consumption is low

**Software implementation:**

- Modelsim
- Xilinx ISE