Implementation of Subthreshold Adiabatic Logic for Ultralow Power Application

Existing system:

             Design and analysis of SAL-based 4-bit CLA are given to show the workability and the feasibility of the proposed logics. After verifying the logical functionality, we implemented an SAL-based standard cell library, consisting of common digital gates, such as buffer/inverter, two-input and three-input functions, complex gates, and special gates like half and full adder, which are necessary to implement the 4-bit CLA. The digital gates of the library are developed at transistor level using ramp type supply voltage as discussed in the previous section. Hence, 22-nm technology file is used in our transistor-level designs which guarantee the manufacturability of our designs under all normal conditions with favorable yields.

These structures resemble either the pull-up or the pulldown network of the static conventional logic. For example, to implement a NAND or a NOR gate, simply the pull-up network can be placed between the supply clock and the output load capacitors, whereas an AND or an OR gate can be implemented using the pull-down network between the supply clock and the output load capacitors. In case of a NAND structure, for every input combination except A = B = 1, the output node voltage will follow the supply clock closely, and we get a triangular output waveform. When A = B = 1 through parallel pMOS transistor, leakage currents will flow as the transistors will behave almost as a constant current source. A very small amount of charge will be stored across the load capacitor, i.e., instead of ground potential, very small voltage will be dropped across the output.

The basic building block of 4-bit CLA, which is also very similar to the conventional structure. Hence, we implemented the sum (S_i) in three stages to avoid delay mismatching with the carry generation. In SAL-based 4-bit CLA, every stage will be controlled by the supply clock. Like the conventional approach, the expression of the i th sum and the (i + 1)th carry output can be given as

Si = Ai ⊕ Bi ⊕ Ci

Ci+1 = Ai Bi + (Ai ⊕ Bi) Ci

Proposed System:

a low-power high speed 5:1 and 7: 1 compressor circuit is proposed for fast digital arithmetic integrated circuits. Based on a new exclusive OR (XOR) and exclusive NOR (XNOR) module, a 5:1 and 7: 1 compressor circuit has been designed.

5: 2 compressor circuit building blocks:

The block diagram of a (5:2) compressor is shown in Fig. 3, which has seven inputs and four outputs. Five of the inputs are the primary inputs x₁, x₂, x₃, x₄ and x₅, and the other two inputs, c_in1 and c _in2 receive their values from the neighboring compressor of one binary bit order lower in significance. All the seven inputs have the same weight. The (5:2) compressor generates an output, sum of the same weight as the inputs, and three outputs, carry, c_out1 and c_out2 weighted one binary order higher. The c_out1 and c_out2 are fed to the neighboring compressor of higher significance.

7: 2 compressor circuit building blocks:

Many methods are utilized to implement 7-2 compressors. It is made up of five full adders and have the delay of 4 full adders All of 7-2 compressors are abided by:

x₁+ x₂+ x₃+ x₄+ x₄+ x₅+ x₆+ x₇+ c_in1+ c_in2=Sum +2.(Carry+ c_out1)+ 4.(c_out2)

A 7-2 compressor gets a1, a2, a3, a4, a5, a6, a7 inputs with weights of one and generates two outputs Sum and Carry with weights of one and two, respectively. Also, it gets two input carry bits Cin1, Cin2 with the same weight of inputs and generates two output carry bits, Cout1, Cout2 with weights of two and four, respectively. As depicted in Fig.6, our proposed design is constructed of a 5-4 arithmetic unit and two 3-2 counters.

Advantages:

• The Power Consumption is reduced for high level of the compressors