## Description

**Existing System:**

The case where the design-under-test is partitioned into logic blocks, and there is a choice with respect to the placement of the built-in test generation logic for these blocks. Fig. 4 illustrates a design that consists of four logic blocks B0, B1, B2 and B3. Horizontal lines stand for scan chains, and vertical lines stand for primary inputs. The built-in test generation method from produces values only for primary inputs, and not for scan chains. The scan chains are used initially for bringing the circuit into a reachable state, and for observing output responses. After initialization, the primary input sequences generated by the built-in test generation logic take the circuit through reachable states. Some of these states are used as initial states for functional broadside tests.

The resulting configuration is illustrated by Fig. 5. In Fig. 5, B0 has n0 = 4 primary inputs, B1 has n1 = 2 primary inputs, B2 has n2 = 3 primary inputs, and B3 has n3 = 2 primary inputs. With n = 4, the LF SR has 4d bits, and four outputs. The gates corresponding to c_{G} are not shown in Fig. 5. Output 0 of the test generation logic drives primary input 0 of B0, B1, B2 and B3. Output 1 of the test generation logic drives primary input 1 of B0, B1, B2 and B3. Output 2 of the test generation logic drives primary input 2 of B0 and B2. Output 3 of the test generation logic drives primary input 3 of B0.

**Disadvantage:**

- to identify the similar characteristics for the less block

** **

**Proposed System:**

In proposed system to use the 9 block for testing of BIST technique. Overall, the built-in test generation method from requires a d*n-bit LFSR, a modulo-L counter, and at most n+1 gates. The initial state s_{init} as well as the seeds are assumed to be scanned in before the application of each primary input sequence. Circular shift requires scan chains of equal lengths. This can be achieved by adding dummy flip-flops to the shorter scan chains.

The primary input sequence A is generated by an LFSR whose states are used as pseudo-random vectors. The LFSR sequence is modified in order to avoid an effect called repeated synchronization, where certain primary input values cause certain state variables to assume the same values repeatedly. The logic for generating the primary input sequence A is illustrated by Fig. 6. For a parameter denoted by d, a distinct set of d bits of the LFSR is used for determining the sequence applied to every primary input. For a parameter denoted by mod, up to mod of the d bits dedicated to each primary input are used for avoiding repeated synchronization. If the value 0 on a primary input synchronizes fewer state variables than the value 1, then the value 0 is preferred. In this case, a mod-input AND gate is used for ensuring that a 0 appears more often than a 1 on this primary input. A mod-input OR gate is used for the primary input if the value 1 synchronizes fewer state variables, and it is thus the preferred value for the primary input. No gate is used if both values synchronize the same number of state variables.

For a circuit with n primary inputs, this method requires an LFSR with d*n bits, and at most one mod-input gate for every primary input. The preferred values of the primary inputs are captured in a primary input cube denoted by c. For a primary input j, c (j) indicates its preferred value, which may be 0, 1 or x. Several primary input sequences are applied by using several different seeds for initializing the LFSR. Each additional sequence results in a different set of functional broadside tests, and helps increase the fault coverage. All the sequences use the same values of the parameters L, d and mod. Consequently, the same logic is used for generating all the tests.

**Advantages:**

- Easy to identify the similar characteristics for the more block

** ****Software implementation:**

- Model sim
- Xilinx 14.2