Obfuscating DSP Circuits via High Level Transformations

Proposed Title : FPGA Implementation of Obfuscating DSP Circuits based approach on Reconfigurable Folded Third order IIR Filter Proposed System: Increase the sampling frequency, and tested cut-off frequency, with low pass, high pass, etc,. Added digital control oscillator, and tested the power level with signal based. Advantages: Reduce the power level Reduced the area size Software implementation: Modelsim Xilinx

Existing system:

The problem of hardware security is a serious concern that has led to a lot of work on hardware prevention of piracy and intellectual property (IP), which can be broadly classified into two main categories:

• Authentication-based approach
• Obfuscation-based approach.

The authentication based approaches include physical unclonable functions (PUFs)-based authentication, digital watermarking, key-locking scheme, and hardware metering. The focus of this paper is on obfuscation, which is a technique that transforms an application or a design into one that is functionally equivalent to the original but is significantly more difficult to reverse engineer. Some hardware protection methods are achieved by altering the human readability of the hardware description language (HDL) code, or by encrypting the source code based on cryptographic techniques. Recently, a number of hardware obfuscation schemes have been proposed that modify the finite-state machine (FSM) representations to obfuscate the circuits. We can observe that:

• Circuits with different functionalities can have a similar structure, and circuits with the same functionality may have very different structures;
• Structural obfuscation can be achieved by high-level transformations; and 3) if the switch instances are invisible to the adversary, then the DSP systems will be harder to reverse engineer, since the functionality of a DSP circuit is not obvious due to obfuscation achieved by high-level transformations. As a result, the adversary who only has knowledge of the structural information but lacks knowledge of the switch instances cannot easily discover the functionality of a DSP circuit.

As an example, we consider a third-order IIR digital filter given by transfer function H(z) = (1 + m2z−1+ m3z−2)/(1 − m0z−2 − m1z−3), as shown in Fig. 1. The coefficients mi corresponds to the multiplication Mi.   We assume the availability of one 1-stage pipelined adder and one 3-stage pipelined multiplier. The filter is folded with folding factor N = 4 using the following folding sets:

M = {M0, M1, M2, M3}

A = {A0, A1, A2, A3}.

Disadvantages:

• Area coverage is high
• Power consumption is high

Proposed system:

High-level transformations alter the structure of a DSP circuit, while maintaining the original functionality. These transformations may lead to architectures whose functionalities are not obvious. Take an extreme case, for example, many filters can be folded into one multiply accumulator (MAC), but their functionalities are not the same. In other words, one MAC with proper switches can implement many different digital filters. Therefore, we can conclude that high-level transformations naturally provide a means to obfuscate DSP circuits both structurally and functionally.

Structural Obfuscation: Any algorithm can be implemented by a family of architectures by using high-level transformations. These architectures enable structural obfuscation where the functionalities of the algorithms can be hidden. This can be considered as a passive model from attacker’s perspective.

Functional Obfuscation: This is realized by encrypting the normal functionality of a DSP circuit with one or more sets of keys. The DSP circuit cannot function correctly without the keys. This corresponds to an active model from attacker’s perspective.

For a folded system to be realizable, the folding equations, DF (U → e V) = Nw (e) − PU + v − u, must be greater or equal to 0 for all the edges in the diagram, where N is the folding factor, w (e) is the number of delays from U to V , PU represents the pipelining level of hardware functional unit for operation type U, and u and v represent the folding orders of U and V , respectively.The folded architecture is shown in Fig. 2.

Secure Switch Design:

The switches generated by high-level transformations are periodic N-to-1 switches. These switches can be implemented as multiplexers, whose control signals are obtained from ring counters (as shown in Fig. 3). Thus, the security of the switch relies upon design of the ring counters such that the outputs of the ring counters can be obfuscated.

A ring counter is often modeled as an FSM. An FSM is usually defined by a 6-tuple (I, O, S, S0, F, G), where S is a finite set of internal states, I and O represent the inputs and
outputs of the FSM, respectively, F is the next-state function, G is the output function, and S0 is the initial state. However, unlike general FSMs, the FSM of a ring counter is input independent, such that it always transits to the next state based on the current state. As a result, the control signal of the switches (i.e., output of the FSM) will be periodic.

Design Methodology:

In this section, we propose a novel DSP hardware protection methodology through obfuscation by hiding functionality via high-level transformations. This approach helps the designer to protect the DSP design against piracy. The detailed design flow is described below.

Step 1: DSP Algorithm: This step generates the DSP algorithm based on the DSP application.

Step 2: High-Level Transformation Selection: Based on the specific application, appropriate high-level transformation should be chosen according to the performance requirement (e.g., area, speed, power, or energy).

Step 3: Obfuscation via High-Level Transformation: Selected high-level transformations are applied simultaneously with obfuscation where variation modes, and different configurations of the switch instances are designed.

Step 4: Secure Switch Design: The secure switch is designed based on the variations of high-level transformations. Note that different configure data could be mapped into the same mode,
which only involves simple combinational logic synthesis.

Step 5: Two-Level FSM Generation: The reconfigurator and the obfuscating FSM are incorporated into the DSP design. The configuration key is generated at this step.

Step 6: Design Specification: This step includes the HDL and netlist generation and synthesis of the DSP system.

The relationship between the obfuscated design and the original design via high-level transformation is shown in Fig. 4. The only difference between the obfuscated design and the original design via high-level transformation is the control of the DSP circuit.

Advantages:

• Area coverage is reduced
• Power consumption is reduced

Software implementation:

• Modelsim
• Xilinx ISE