Proposed Title :
FPGA Implementation of Reliable CRC Error Detection for Versatile and Scalable Digit Serial/Parallel Finite Field Multipliers for Cryptography Applications
Improvement of this Project:
To design the Versatile and Scalable Digit Serial/Parallel Multiplier Architecture for Finite Field
To design the Reliable CRC implementation using Digit serial Multiplier
· To design GF(23) = 8-Bit and GF(25) = 32-Bit Digit serial multiplier with CRC based Error detection.
In the featuring applications in cryptography and error detection codes, finite filed multiplication has attracted considerable attention in the research. This cryptography arithmetic procedure is a complicated, expensive and time consuming work, its requiring millions of gates. In this case study of cryptographic algorithm, research of this work suggest efficient hardware design based on cyclic redundancy check (CRC) as a error detection system for all cryptographic applications. With applications to cryptography, this paper introduce an architecture for digit serial multiplication in finite fields GF(2m). Multiplication and degree reduction stages are interleaved in the proposed system, which employs polynomial basis representation. An M-bit multiplier may be used for any binary field of order and works with any irreducible polynomials. Thus, the Versatile and Scalable Digit Serial/Parallel Multiplier Architecture for Finite Field will integrated with Reliable CRC implementation and design GF(23) = 8-Bit and GF(25) = 32-Bit based CRC Error detection. This work was developed in Verilog HDL and synthesized in Vertex-5 FPGA and compared all the parameters in terms of area, delay and power.
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Reliable CRC Based Error Detection Constructions for Finite Field Multipliers With Applications in Cryptography
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