FPGA Implementation of High Performance Accurate and Approximate Singed and Unsigned Multipliers using Structure of LUT configurations
Improvement of this Project:
To design the Accurate and Approximate Signed and Unsigned Multiplier for 8-bit configuration, and to re-modified the LUT6 architecture using single LUT5 with multiplexers instead of dual LUT5 with multiplexers.
In a recent application utilizing the arithmetic operations of multiplication and division are frequently employed in a range of applications, including image/video processing and machine learning. DSP blocks, which are available from FPGA suppliers, are high-performance multipliers. In addition to being restricted in number and having fixed placements on FPGAs, these multipliers may also cause extra routing delays and may be inefficient for lower bit-width multiplications, which can result in increased power consumption. Soft IP cores that are designed for multiplication are thus provided by FPGA suppliers as an extra feature. Although these soft multiplier IP cores for FPGAs have improved in recent years, we propose in this paper that they still need improved designs in order to give excellent performance while conserving resources. This is achieved through the development of generic area-optimized, low-latency accurate and approximate soft-core multiplier architectures that take advantage of the underlying architectural features of FPGAs, such as look-up table (LUT) structures and fast carry chains, in order to reduce the overall critical path delay and resource utilization of multipliers. To construct the Accurate and Approximate Signed and Unsigned Multiplier for 8-bit configuration utilizing the suggested technique of this study, and to re-modified the LUT6 architecture by employing a single LUT5 with multiplexers instead of a dual LUT5 with multiplexers. At the end of the process, this work was designed in Verilog HDL and synthesized in Xilinx software, and all of the parameters were compared in terms of area, delay, and power.
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High Performance Accurate and Approximate Multipliers for FPGA based Hardware Accelerators
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