RoBA Multiplier A Rounding Based Approximate Multiplier for High Speed yet Energy Efficient Digital Signal Processing

Description

Proposed Title : FPGA Implementation of High Performance and Low Power FIR Filter Design using Rounding Based Approximate Multiplier ( RoBA Multiplier) Proposed System: In FIR filter designed, will used design any multipliers, if last frequent years, the MCM technique will used, as a proposed of FIR filter design, but the drawback is MCM technique will not work both thing of signed and un-signed operation, so it will we need to design separate MCM for signed and unsigned multiplication. So here, we are proposed a MCM with Rounded based approximate multiplier that includes both signed and unsigned operation in single multiplier, this multiplier will implemented in FIR Filter, and shown the efficiency of area, power and delay. Software implementation: Modelsim Xilinx

Existing System:

Filter coefficients very often remain constant and known a priori in signal processing applications. This feature has been utilized to reduce the complexity of realization of multiplications. Several designs have been suggested by various researchers for efficient realization of FIR filters (having fixed coefficients) using distributed arithmetic (DA) and multiple constant multiplication (MCM) methods. DA-based designs use lookup tables (LUTs) to store pre computed results to reduce the computational complexity. The MCM method on the other hand reduces the number of additions required for the realization of multiplications by common sub expression sharing, when a given input is multiplied with a set of constants. The MCM scheme is more effective, when a common operand is multiplied with more number of constants. Therefore, the MCM scheme is suitable for the implementation of large order FIR filters with fixed coefficients. But, MCM blocks can be formed only in the transpose form configuration of FIR filters.

Block-processing method is popularly used to derive high-throughput hardware structures. It not only provides throughput-scalable design but also improves the area-delay efficiency. The derivation of block-based FIR structure is straightforward when direct-form configuration is used [16], whereas the transpose form configuration does not directly support block processing. But, to take the computational advantage of the MCM, FIR filter is required to be realized by transpose form configuration. Apart from that, transpose form structures are inherently pipelined and supposed to offer higher operating frequency to support higher sampling rate.

Disadvantages:

• Separate Multiplier design for Signed and Unsigned Operation
• More logic size
• More Power and delay

Proposed System:

Finite Impulse response (FIR) digital filter is widely used in several digital signal processing application, such as speech processing, loud speaker equalization, echo cancellation, adaptive noise cancellation, and various communication application, including software-define radio (SDR) and so on. Many of these application require FIR filter of large order to meet the stringent frequency specification. Very often these filters need to support high sampling rate for high-speed digital communication. The number of multiplication and additions required for each filter output, however, increases linearly with the filter order. Since there is no redundant computation available in the FIR filter algorithm, real-time implementation of a large order FIR filter in a resource constrained environment is a challenging task. Filter coefficients very often remain constant and known a priori in signal processing application. This feature has been utilized to reduced the complexity of realization of multiplications.

In FIR filter designed, will used design any multipliers, if last frequent years, the MCM technique will used, as a proposed of FIR filter design, but the drawback is MCM technique will not work both thing of signed and un-signed operation, so it will we need to design separate MCM for signed and unsigned multiplication. So here, we are proposed a MCM with Rounded based approximate multiplier that includes both signed and unsigned operation in single multiplier, this multiplier will implemented in FIR Filter, and shown the efficiency of area, power and delay.

PROPOSED APPROXIMATE MULTIPLIER:

The main idea behind the proposed approximate multiplier is to make use of the ease of operation when the numbers are two to the power n (2n). To elaborate on the operation of the approximate multiplier, first, let us denote the rounded numbers of the input of A and B by Ar and Br, respectively. The multiplication of A by B may be rewritten as

A × B = (Ar − A) × (Br − B) + Ar × B + Br × A − Ar × Br. (1)

The key observation is that the multiplications of Ar × Br, Ar ×B, and Br ×A may be implemented just by the shift operation. The hardware implementation of (Ar − A) × (Br − B), however, is rather complex. The weight of this term in the final result, which depends on differences of the exact numbers from their rounded ones, is typically small. Hence, we propose to omit this part from (1), helping simplify the multiplication operation. Hence, to perform the multiplication process, the following expression is used:

A × B ∼= Ar × B + Br × A − Ar × Br. (2)

Thus, one can perform the multiplication operation using three shift and two addition/subtraction operations. In this approach, the nearest values for A and B in the form of 2n should be determined. When the value of A (or B) is equal to the 3 × 2p−2 (where p is an arbitrary positive integer larger than one), it has two nearest values in the form of 2n with equal absolute differences that are 2p and 2p−1. While both values lead to the same effect on the accuracy of the proposed multiplier, selecting the larger one (except for the case of p = 2) leads to a smaller hardware implementation for determining the nearest rounded value, and hence, it is considered in this paper. It originates from the fact that the numbers in the form of 3 × 2p−2 are considered as do not care in both rounding up and down simplifying the process, and smaller logic expressions may be achieved if they are used in the rounding up. The only exception is for three, which in this case, two is considered as its nearest value in the proposed approximate multiplier.

It should be noted that contrary to the previous work where the approximate result is smaller than the exact result, the final result calculated by the RoBA multiplier may be either larger or smaller than the exact result depending on the magnitudes of Ar and Br compared with those of A and B, respectively. Note that if one of the operands (say A) is smaller than its corresponding rounded value while the other operand (say B) is larger than its corresponding rounded value, then the approximate result will be larger than the exact result. This is due to the fact that, in this case, the multiplication result of (Ar − A) × (Br − B) will be negative. Since the difference between (1) and (2) is precisely this product, the approximate result becomes larger than the exact one. Similarly, if both A and B are larger or both are smaller than Ar and Br, then the approximate result will be smaller than the exact result.

Finally, it should be noted the advantage of the proposed RoBA multiplier exists only for positive inputs because in the two’s complement representation, the rounded values of negative inputs are not in the form of 2n. Hence, we suggest that, before the multiplication operation starts, the absolute values of both inputs and the output sign of the multiplication result based on the inputs signs be determined and then the operation be performed for unsigned numbers and, at the last stage, the proper sign be applied to the unsigned result. The hardware implementation of the proposed approximate multiplier is explained next.

Advantages:

• Common Multiplier design for Signed and Unsigned Operation
• Less Logic size
• Less Power and delay