Proposed Title :
FPGA Implementation of QPSK Modulator
Improvement of this Project:
- To reduced the area power and delay, and updated the architecture with demodulator, LPF and BPF
- Xilinx 14.2
QPSK Modulation, here the input will provided as a Binary information, and its converted into 2Bit serial to parallel form, then the 2Bit form will provided to voltage control oscillator scheme of COS and SIN signal generator with Encode TX pulse, and its multiplied to carrier frequency then the signal to be added before transmission output. The QPSK modulation is determined a format of phase changes from previous signal. In the Quadrature modulation will have four possible states such a Hence this each states which is represents two information bits, it splitting of binary patterns as same of QPSK modulation technique, it shifter the phase to about depending upon the requirement.
In the Modulation of wireless communication technology will used to transfer the data by changing the frequency, amplitude and phase of the carrier signals, with this digital data of modulation scheme it will need to map the corresponding signals for example in the binary modulation ‘0’ and ‘1’ will be map to the time(t) of waveforms. In modulation each input data will form a group of bits to the form of M=2b which is corresponding to M-ary modulation for M>2. The Quadrature Phase shift keying is also one of the modulation technique of M-ary modulation M=4, with this M will denoted as symbol of four distinct waveforms of different phase. The QPSK Modulation will achieve the same bandwidth, data throughput, bit error rate, power efficiency with compare to the QPSK. Four symbols of M=4 is located with equal spacing.
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QPSK Modulator on FPGA
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