Proposed Title :
Design of Low Complexity and Efficient Reconfigurable Digital IF Filter using Multi Stage Filter Bank.
Improvement of this Project:
To Design a reconfigurable Digital IF Filter with variable center frequency and bandwidth.
The centre frequency can be varied from the 500MHZ to 1GHZ and filter bandwidth can be selective to one of 10MHZ, 15MHZ and 20MHZ frequency level.
Design all the Multipliers in Truncated method
Recently, mobile communications has to ensure a wide frequency band to transmit a large amount of data with a high data rate. It is evolving into advanced communications such as LTE (4G services) to realize large amounts of data and fast transmission speed, and now has 5G mobile communications in the spotlight. Therefore, spectrum allocation for mobile communications is becoming increasingly complicated. In base stations and repeaters, spectrum efficiency is maximized by using filters to minimize the interference of adjacent frequencies. The filters are employed to suppress crosstalk between adjacent signals, to minimize interference between transmission and reception frequencies, and to suppress spurious emissions caused by inter modulation in the system.
General base stations and repeaters in mobile communications adopt super-heterodyne receivers, which eliminate adjacent bands at intermediate frequency (IF). This system generally utilizes analogue IF band pass filters to minimize various frequency interference between heterogeneous services, adjacent service providers, and transmission and reception. These analog filters include an LC filter and a surface acoustic wave (SAW) IF filter. Recently, SAW filters have been replaced with digital IF filters based on finite impulse response (FIR). The SAW filter has high frequency stability and selectivity. However, when repeaters and base stations want to change the center frequency and bandwidth for new service adaptation, a new SAW filter should be developed and embedded due to its fixed frequency characteristics. As a result, system development is needed for the changed frequency environment or is supposed to adopt multiple SAW filters of two or more types, which causes both the increase of system costs and the delay in service opening. For these reasons, development of a variable digital filter responding to changeable frequency environments is required.
Variable digital FIR filters have been researched to be applied to various specifications of application services. Therefore, in this brief, we propose a reconfigurable digital IF filter that can adjust both the center frequency and bandwidth while maintaining high frequency selectivity as an existing fixed SAW filter. Since the digital band pass filter of IF band needs to support high sampling rate, a large number of taps are required for high frequency selectivity, which results in increasing hardware complexity significantly. Various digital FIR structures with low complexity have been proposed. According to this tendency, in this brief, we propose a filter bank lowering the sampling rate in order to reduce the hardware complexity of a single digital band pass filter. In addition, we also propose a band pass filter with a recursive multi-stage structure working at a lower sampling rate.
- The existing SAW filters does not have the variable center frequency, it only has a fixed frequency.
- SAW filters produces the more delay in service openings.
Due to limited frequency resources, new services are being applied to the existing frequencies, and service providers are allocating some of the existing frequencies for newly enhanced mobile communications. Because of this frequency environment, repeater and base station systems for mobile communications are becoming more complicated, and frequency interference caused by multiple bands and services is getting worse. The IF (Intermediate Frequency) Filters with high selectivity is used to reduce the interference between the different frequency range. Therefore, the heterodyne receivers uses the IF filter. In mobile communication the repeaters and the base station cannot actively cope because, it has fixed frequency range. Therefore, this paper proposes the new design concept of low complexity and efficient reconfigurable digital IF filters using multi stage filter bank. The multi stage filter bank of the proposed digital IF filters lowering the sample rate in order to reduce the hardware complexity. The existing system of digital IF filters uses the concept of SAW(surface acoustic wave) IF filter, it has high frequency stability and selectivity but, it does not have variable centre frequency. The SAW IF filters has the fixed frequency level only. Therefore the proposed system of digital IF filters uses the concept of multi stage filter bank in order to reduces the hardware complexity and better performance. The proposed digital IF filters uses the different centre frequency from the range of 500MHZ to 1GHZ and filter bandwidth can be selective to one of 10MHZ, 15MHZ and 20MHZ frequency level. The proposed digital IF filter reduces the complexity of adders and multipliers. Finally, The Digital IF filter using multi stage filter bank in VHDL and synthesized in the XILINX FPGA-S6LX9 and shown the comparison in terms of area, power and delay reports.
Digital IF Filter System
A digital FIR filter can change its center frequency and bandwidth by adjusting filter coefficients. In this brief, we design a digital IF filter that sets coefficients from a software to change both the center frequency and the bandwidth. Since the hardware structure is likely to be fixed and has less flexibility,the maximum number of taps has to be determined first. The maximum number of taps can be given from the required frequency response of filter, which is a function of a sampling rate, transition width (frequency gap between the end of pass band and the start of stop band), ripple in the pass band, and suppression in the stop band. In this brief, we design a filter depending on the specification of Table I according to the ITU standards required for 3G and 4G mobile communication systems. The maximum number of taps needed in the filter can be obtained by using the MATLAB Filter Design & Analysis (FDA) tool. Since the required number of taps increases in proportion to the sampling rate, the maximum number of taps is given at the highest center frequency of IF band.
The digital IF filter requires a large number of taps, because the filter has to meet the specifications in Table while working at a high sampling rate for high frequency selectivity. This causes the hardware resources of filter more complex. Therefore, in order to reduce the hardware complexity of filter, we propose both a filter bank structure using a digital down converter (DDC) and a digital up-converter (DUC) and a band pass filter structure using a multi-stage scheme.
Filter bank with a DDC and a DUC
In order to reduce the hardware complexity of digital IF filter, simple approach is to decrease sampling rate, this makes a filter bank structure adopt a DDC and a DUC. Since the number of taps highly depends on the sampling rate, to have the sampling rate lower at the same bandwidth is to reduce the complexity of filter effectively. The filter bank consists of a DDC, decimation (down sampling), and interpolation (up sampling), and a DUC. It includes four image rejection filters (IRFs) to reject images that occur during down-conversion or up conversion. As shown in above Figure prior to the band pass FIR filter, there are the DDC to lower the center frequency and decimation to reduce sampling rate, ????????????????. As the sampling rate is lowered due to the decimation process, ????????????????/????????, the same filter performance can be achieved with fewer taps than an existing single digital filter. After band pass filtering, up sampling is performed to recover the sampling rate, ????????????????, and the center frequency is moved to the original position through the DUC. Four IRFs with a few taps have to be deployed both before and after the DDC and DUC to remove images.
For the same frequency response of filter, the number of taps (N) can be decreased to N/s by reducing the sampling rate to 1/s in decimation. Because of digitized down-converting, however, the decimation value, s, in the proposed system has to have a natural value and be limited by several system parameters such as IF carrier frequency and bandwidth in commercial repeaters. A digital IF filter has to works in the given IF carrier frequency (from 10MHz to 65MHz), which has been generally used for analog IF SAW filters in commercial repeaters. For the given sampling rate and bandwidth, s is obtained, and then the optimized BPF can be designed for specifications required in the standard. For each IRF, the minimum number of taps is estimated in MATLAB simulation in order only to reject images. Since the filtered data of BPF is not corrupted through the image rejection process and the desired data are far away from images, the required number of taps for IRFs in the filter bank is very small as shown in Figure. The low cost paid for IRFs makes the total number of taps effectively reduced. In this approach, the complexity of proposed filter can be reduced considerably.
We use the MATLAB FDA tool to generate the coefficient of filters in the proposed filter bank for the specifications given in Table. The complexity of proposed filter using a filter bank can be reduced by 16.42% and 19.85% with respect to the number of multipliers and the adders, respectively, compared with the single digital filter without a filter bank.
Digital IF band pass filter with multi-stage structure
In the band pass filter, which is a digital FIR filter working at the down sampling rate, it is possible to perform parallel operation when maintaining the original clock speed even after decimation process. The above Figure shows a block diagram of the proposed multi-stage structure. In the proposed multi-stage structure, the original structure of FIR filter is divided into s same structures by the ratio of decimation, s. The original n order FIR filter requires n-1 adders and n/2. When the data stream is decimated by the ratio of s, the speed of data fed into the filter is also reduced to one-s-th. The regular filter unit with 1/s adders and 1/s multipliers can perform the same work as the original n-order FIR filter by repeating filter operation s times recursively at the original working speed. With this approach, both the number of adders and multipliers can be reduced by 1/s compared to an existing band pass FIR filter without a multistage structure.
The number of multipliers and adders of an existing single IF filter and the proposed IF filter using both the filter bank and the multi-stage structure. When s is 2, the hardware costs of multipliers and adders are reduced by 38.81% and 41.57%, respectively. The reduction ratio of proposed IF filter is higher in terms of hardware costs when the multi-stage structure is employed compared to the filter bank structure.
- IF Filter is used to minimize the interference between the frequencies.
- The IF Filters with variable centre frequency and bandwidth achieves high selectivity.
- The filter bank lowering the sample rate in order to reduce the hardware complexity.
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Design of Reconfigurable Digital IF Filter with Low Complexity
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