To develop and Implement Low Power, High Speed VLSI for Processing Signals using Multi rate Techniques Low Power Divider Using Vedic Mathematics

Existing System:

Interest in signal processing long predates computers. As long as people have tried to send or receive information through electronic media, such as telegraphs, telephones, television, radar, etc., there has been the realization that these signals may be affected by the system used to acquire, transmit, or process them. Sometimes these systems are imperfect and introduce noise, distortion, or other artifacts. Understanding the effects these systems have and finding ways to correct them is the foundation of signal processing. There are many types of signal processing. Among those Digital signals processing is more efficient and widely used.

The presented methodology provides a systematic way to derive circuit technique for high speed operation at a low supply voltage. It is commonly accepted that low power circuits are very slow circuits and high speed circuits required very high power consumption. In many practical application of digital signal processing, there is a problem of changing the sampling rate of a signal, either increasing it or decreasing it by some amount.

“Upsampling” is the process of inserting zero-valued samples between original samples to increase the sampling rate. (This is called “zero-stuffing”.) Upsampling adds to the original signal undesired spectral images which are centered on multiples of the original sampling rate.

Upsampler consist of Shift register, D F/F and Multiplexer. Scaling process has been done then it is simulated and synthesized on cadence platform. Obviously, some techniques applied to high speed circuits needed larger power consumption. However, it is directed that many techniques are used to reduced power dissipation in high speed circuits.

“Interpolation”, in the DSP sense, is the process of Upsampling followed by filtering. (The filtering removes the undesired spectral images.) As a linear process, the DSP sense of interpolation is somewhat different from the “math” sense of interpolation, but the result is conceptually similar: to create “in-between” samples from the original samples. The result is as if you had just originally sampled your signal at the higher rate.

Proposed System:

Multirate simply means “multiple sampling rates”. A multirate DSP system uses multiple sampling rates within the system. Whenever a signal at one rate has to be used by a system that expects a different rate, the rate has to be increased or decreased, and some processing is required to do so.

The most immediate reason is when you need to pass data between two systems which use incompatible sampling rates. For example, professional audio systems use 48 kHz rate, but consumer CD players use 44.1 kHz; when audio professionals transfer their recorded music to CDs, they need to do a rate conversion. But the most common reason is that multirate DSP can greatly increase processing efficiency (even by orders of magnitude!), which reduces DSP system cost.

The most immediate reason to decimate is simply to reduce the sampling rate at the output of one system so a system operating at a lower sampling rate can input the signal. But a much more common motivation for decimation is to reduce the cost of processing: the calculation and/or memory required to implement a DSP system generally is proportional to the sampling rate, so the use of a lower sampling rate usually results in a cheaper implementation.

Down sampler consist of D F/F, clock generator and multiplexer. Loosely speaking, “decimation” is the process of reducing the sampling rate. In practice, this usually implies low pass-filtering a signal, then throwing away some of its samples.”Downsampling” is a more specific term which refers to just the process of throwing away samples, without the low pass filtering operation. Throughout this FAQ, though, we’ll just use the term “decimation” loosely, sometimes to mean “downsampling”.

The down samplers associated with increasing delay elements can be implemented by a commutator switch model moving in counter-clockwise direction at the input side. This results in sample rate reduction or decimation.