A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors

Proposed System:

Hard decision detection scheme:

The PDP algorithm in this paper, consisting of three stages, is illustrated in Fig. 6, where P =M*M_t, H (m) is the channel matrix for the m-th sub-carrier and the superscript H is the Hermitian transform. These stages are described in the sequel.

First Stage: An MMSE equalizer1is utilized to produce the initial estimate of the symbol sequence by reversing the channel effect for each sub-carrier to estimate the transmitted FD signals. Subsequently, an M-point IDFT operation is executed on all sub-carriers to find time-domain signals. Therefore, the effect of the channel and the DFT are taken into account independently in this stage of the detection process. The IDFT outputs (i.e., z) are then mapped to the constellation points and grouped to produce M*M_t symbols in the initial estimate, z^.

Second Stage: In order to improve the initial MMSE estimate, a number of symbols in the initial estimate are selected. For these selected symbols, extra possible candidates in the constellation are explored to see if they result in a better estimate. The selected symbols are, in fact, the ones that were initially more prone to error, called the “erroneous symbols.” In order to find the erroneous symbols, a reliability metric (i.e., the error probability (EP) metric) is defined for each symbol representing its error probability. To calculate the EP metric, each symbol in the initial estimate is replaced with all other possible constellation points, with their corresponding Euclidean Distances (ED) calculated while other symbols remain unchanged. Then the lowest ED among them is defined as the EP metric for that specific symbol. It can be shown that the symbols with the lowest EP metric are the least reliable ones.

Third Stage: In the conventional ML-PDP, an ML detection is performed on a subset of the initial estimate (i.e., N_e the erroneous symbols) in order to improve the result. However, the complexity of this process grows exponentially with the number of selected symbols (i.e., requires Q^Ne ED calculations).

The hard detection VLSI architecture:

According to this architecture, one MMSE block and M_t number of M-point IDFT blocks are utilized. In each clock cycle, the MMSE block generates M_t outputs, which are kept in registers via the serial-to-parallel block. After M clock cycles, an M-point IDFT is executed on these outputs. Since efficient implementations of the MMSE and the IDFT block already exist in the literature, the focus of this paper is geared toward the realization of the second and third stages.

The architecture of the second and third stages of the proposed scheme is depicted in Fig. 8, where the dashed lines denote a number of the pipelining stages. The inputs of the architecture are the channel coefficients, the outputs of the MMSE detector, and the received FD signals at the receiver. In fact, the “H” inputs represent the values of all the terms in H_eff the t-th row in at the t-th clock cycle, the “Z” inputs are the outputs of the first stage, and the “Y” input represents the t-th element in Y at the t-th clock cycle. The architecture performs the detection in clock cycles.

Soft detection scheme:

While the proposed structure provides a superior BER performance compared to the conventional MMSE receivers, a soft-coded system is proposed that complies with advanced wireless standards. In a coded system, the transmitter encodes the message by using an error-correcting code. At the receiver, the decoding is performed based on the extrinsic log-likelihood ratios (LLR) calculated by the MIMO detector. The LLRs are in fact the soft information representing the reliability of the detection. In contrast to a hard MIMO detector where a hard decision is made for each bit, a soft MIMO detector generates a value for each bit representing the probability of its being one or zero. In order to enhance the performance of the coded system, the MIMO detector will have to generate a soft decision based on the transmitted symbols. In a Q-ary QAM modulation, LLR values must be calculated for all bits in each symbol resulting in log₂ Q * P number of LLR calculations for P symbols.

Advantages:

• Reduce the complexity of hardware implementation
• Reduce the size