Proposed Title :
FPGA Implementation of Dadda Multiplier using Gaussian Image Noise Reduction Method
Improvement of this Project:
- To provide the proposed (luminance, chrominance ) image input from the MATLAB GUI, of Image to hex conversion, and verify the output of the image in MATLAB GUI, and also compared the area, power, and delay.
- Xilinx 14.2
In this paper, we propose four 4:2 compressors, which have the flexibility of switching between the exact and approximate operating modes. In the approximate mode, these dual-quality compressors provide higher speeds and lower power consumptions at the cost of lower accuracy. Each of these compressors has its own level of accuracy in the approximate mode as well as different delays and power dissipations in the approximate and exact modes. Using these compressors in the structures of parallel multipliers provides configurable multipliers whose accuracies (as well as their powers and speeds) may change dynamically during the runtime. The proposed multiplier saves few adder circuits in partial products, and this proposed multiplier is evaluated with an image processing application. In existing thing, to using this multiplier to design image processing evaluation on only luminance based application, but here the proposed work is modified with Gaussian noise reduction with luminance and chrominance based application, this design to implemented in VHDL, and synthesized in Xilinx S6LX9 FPGA and shown the power, area and delay reports.
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Dual Quality 4:2 Compressor for Utilizing in Dynamic Accuracy Configurable Multipliers
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