Proposed Title :
FPGA Implementation of High Speed and High Image Resolution Sobel Edge Detection
Improvement of this Project:
Improved the image resolution up to 1024 x 1024 pixel size, and find the SSIM and PSNR values of standard images.
Reduce the number of logic size in overall hardware architecture and proved the performance analysis’s using Zynq FPGA.
Image processing is an important task in all data processing applications such as medical imaging, remote sensing, microscopic imaging and so on. Thus edge detection of an image is the primary and significant step is lower level image processing. The edge detection technique finds significant applications in various fields which mainly includes object tracking, image analysis, image segmentation etc. The brief analysis of this work describes a Sobel filter based edge detection algorithm design for Field Programmable Gate Array (FPGA), it will provide honest scope of similarity over software implementation. Similarly it provide very less deterioration in high level of image noise. This paper mainly focuses on sobel operator based edge detection for real time applications using FPGA. Due to the better noise sensitivity as compared to other operator sobel operator is mainly used. There is much reduction in the FPGA resources which reduces the area of the FPGA. The proposed model precisely detects edges of an image. The proposed architecture of sobel edge detection will designed in 1024×1024 image resolution and this paper analysis the logic size, area and power consumption using Zynq FPGA.
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FPGA implementation of low power and high speed image edge detection algorithm
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