Proposed Title :
FPGA Implementation of Gaussian noise reduction using Approximate Multiplier with Altered Partial Products
- The existing architecture of luminance (y) Gaussian noise reduction using Approximate multiplier with altered partial products, to modified with luminance (y) and chrominance (cb, cr) Gaussian noise reduction using Approximate multiplier with altered partial products.
The proposed hardware multiplier reduced the complexity and also truncated widely employed in fixed width multiplier design. Here the proposed multiplier approximate technique is fully focus on accumulation of partial products, which is crucial in terms of power consumption. The proposed multiplier saves few adder circuits in partial products, and this proposed multiplier is evaluated with an image processing application. In existing thing, to using this multiplier to design image processing evaluation on only luminance based application, but here the proposed work is modified with luminance and chrominance based application, this design to implemented in VHDL, and synthesized in Xilinx S6LX9 FPGA and shown the power, area and delay reports.
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Design of Power and Area Efficient Approximate Multipliers
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