Design of Power and Area Efficient Approximate Multipliers

Description

Existing System:

Previous works on logic complexity reduction focus on straightforward application of approximate adders and compressors to the partial products. In this brief, the partial products are altered to introduce terms with different probabilities. Probability statistics of the altered partial products are analyzed, which is followed by systematic approximation. Simplified arithmetic units (half-adder, full-adder, and 4-2 compressor) are proposed for approximation. The arithmetic units are not only reduced in complexity, but care is also taken that error value is maintained low. While systemic approximation helps in achieving better accuracy, reduced logic complexity of approximate arithmetic units consumes less power and area. The proposed multipliers outperforms the existing multiplier designs in terms of area, power, and error, and achieves better peak signal to noise ratio (PSNR) values in image processing application.

Error distance (ED) can be defined as the arithmetic distance between a correct output and approximate output for a given input. In approximate adders are evaluated and normalized ED (NED) is proposed as nearly invariant metric independent of the size of the approximate circuit. Also, traditional error analysis, MRE is found for existing and proposed multiplier designs.

Disadvantages:

• Not provided the output with Chrominance
• More Area, and Power
• Low Performance

Proposed System:

The proposed hardware multiplier reduced the complexity and also truncated widely employed in fixed width multiplier design. Here the proposed multiplier approximate technique is fully focus on accumulation of partial products, which is crucial in terms of power consumption. The proposed multiplier saves few adder circuits in partial products, and this proposed multiplier is evaluated with an image processing application. In existing thing, to using this multiplier to design image processing evaluation on only luminance based application, but here the proposed work is modified with luminance and chrominance based application, this design to implemented in VHDL, and synthesized in Xilinx S6LX9 FPGA and shown the power, area and delay reports.

Implementation of multiplier comprises three steps: generation of partial products, partial products reduction tree, and finally, a vector merge addition to produce final product from the sum and carry rows generated from the reduction tree. Second step consumes more power. In this brief, approximation is applied in reduction tree stage. A 8-bit unsigned1 multiplier is used for illustration to describe the proposed method in approximation of multipliers. Consider two 8-bit unsigned input operands α = 7 m=0 αm2m and β = 7 n=0 βn2n. The partial product am,n = αm · βn in Fig. 1 is the result of AND operation between the bits of αm and βn.

From statistical point of view, the partial product am,n has a probability of 1/4 of being 1. In the columns containing more than three partial products, the partial products am,n and an,m are combined to form propogate and generate signals as given in (1). The resulting propogate and generate signals form altered partial products pm,n and gm,n. From column 3 with weight 23 to column 11 with weight 211, the partial products am,n and an,m are replaced by altered partial products pm,n and gm,n.

pm,n = am,n + an,m

gm,n = am,n · an,m.                                                 (1)

The probability of the altered partial product gm,n being one is 1/16, which is significantly lower than 1/4 of am,n. The probability of altered partial product pm,n being one is 1/16 + 3/16 + 3/16 = 7/16, which is higher than gm,n. These factors are considered, while applying approximation to the altered partial product matrix.

APPLICATION—IMAGE PROCESSING

Geometric mean filter is widely used in image processing to reduce Gaussian noise [13]. The geometric mean filter is better at preserving edge features than the arithmetic mean filter. Two 16- bits per pixel gray scale images with Gaussian noise are considered. 3 × 3 mean filter is used, where each pixel of noisy image is replaced with geometric mean of 3 × 3 block of neighboring pixels centered around it. The algorithms are coded and implemented in MATLAB. Exact and approximate 16-bit multipliers are used to perform multiplication between 16-bit pixels. PSNR is used as figure of merit to assess the quality of approximate multipliers. PSNR is based on mean-square error found between resulting image of exact multiplier and the images generated from approximate multipliers. Energy required by exact and approximate multiplication process while performing geometric mean filtering of the images is found using Synopsys Primetime. Further, exact multiplier is voltage scaled from 1 to 0.85 V (VOS), and its impact on energy consumption and image quality is computed. The noisy input image and resultant image after denoising using exact and approximate multipliers, with their respective PSNRs and energy savings in μJ are shown in Figs. 4 and 5, respectively. Energy required for exact multiplication process for image-1 and image-2 is 3.24 and 2.62 μJ , respectively. Although ACM1 has better energy savings compared to Multiplier1, Multiplier1 has significantly higher PSNR than ACM1. Multiplier2 shows the best PSNR among all the approximate designs. Multiplier2 has better energy savings, compared to ACM2, PPP, SSM, UDM, and VOS. The intensity of image-1 being mostly on the lower end of the histogram causes poor performance of ACM multipliers. As the switching activity impacts most significant part of the design in VOS, PSNR values are affected.

• Provide the output with luminance and chrominance
• Less Area and Power
• High Performance