Proposed Title :
FPGA Implementation of XOR-MUX Full adder
based Approximate 4-2 Compressor (UCAC1, UCAC2, UCAC3) and Error Correcting
Module (ECM) for Low Power Approximate Multipliers
Improvement of this Project:
To integrated XOR-MUX Full Adder in the Approximate Multiplier instead of Conventional Multiplier, and hence proved with three comparisons of UCAC1, UCAC2, UCAC3 and ECM.
To design the Image Multiplication with 256×256 image and calculated PSNR and SSIM values for all the Approximate Multipliers.
Approximate computation is being used provisionally in some digital signal processing system that have an inherent tolerance for incorrect computing performance. The estimated arithmetic blocks are used in them to increases the electrical efficiency of these circuits. A multiplier is a basic fundamental unit of computing arithmetic blocks. Furthermore, 4-2 compressor are commonly used in parallel multipliers to improve the compression process of partial product reduction method. Here, three new estimated 4:2 compressor are proposed with UCAC1, UCAC2, UCAC3, where used in 8-bit multipliers in this method. Meanwhile, an error correcting module (ECM) is presented to improve the error efficiency of the proposed 4:2 compressor with the estimated multiplier. In this proposed method, the number of estimated 4:2 compressor will reduced the number of partial products and resolve the compression errors with support of error correction module. Similarly, the proposed work of this design will integrated with XOR-MUX full adder to reduce more logic gates in the Approximate multiplier. Finally, this work was designed in Verilog HDL, and synthesized in Xilinx Vertex-5 FPGA, and compared all the parameters in terms are area, delay and power.
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