Proposed Title :
Area, Delay and Energy Efficient FAST and BRIEF Detector with using Carry Select Adder
Improvement of this Project:
To reduce the number of logic size in FAST and BRIEF image smoothing method with using area, delay and power efficient carry select adder.
To synthesize this two different design at Xilinx FPGA and hence proved the comparisons of slice register, slice LUT, occupied slice, delay and power.
In a recent convergence of highly stable image processing application will have sustain FAST corners and BRIEF descriptors method. In this FAST and BRIEF architecture will have more complexity in arithmetic operations to perform summation of accumulation on streaming pixels for the smoothing operations. Therefore, this work present a novel detector for computing FAST BRIEF feature with using area, delay and energy efficient carry select adder, thus it will decrease the quantity of logic gates in FPGA implementation compare to obtainable ripple carry adder based architecture. Hence, implemented a 256 x 256 grayscale image in smoothing operation of FAST and BRIEF architecture, and proved the performance of PSNR, SSIM. Similarly this proposed architecture will have synthesized in Xilinx FPGA and compared all the parameters in terms of area, delay and power.
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Area-Time Efficient Streaming Architecture for FAST and BRIEF Detector
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