Proposed Title :
FPGA Implementation of Highly efficient Reconfigurable Constant Coefficient Multiplier (RCCM) using Carry Select Adder
Improvement of this Project:
To design the 32-Bit Size of Build Reconfigurable constant coefficient Multiplier of ADD-2, ADD-3 and ADD-4 using area delay and power efficient carry select adder.
Compared this proposed work to existing method in Xilinx FPGA.
A deep learning application will have very low precision arithmetic operation in field programmable gate array, it will take more silicon area. Thus, this proposed work introduced a reconfigurable constant coefficient multipliers (RCCMs), it will provide better performance in silicon area and utilizing low precision in arithmetic applications. RCCMs aggregate input value by a narrow selection of coefficients using only adders, subtractors, bit shifts and multiplexers. In this proposed method to minimized the logic area in RCCM technique of arithmetic operations, by using low power and area efficient carry select adder, it will reduce more silicon area in deep learning applications. Similarly, this work compared the existing method of ripple carry adder based RCCM technique using Xilinx FPGA, on different sizes of RCCM such as ADD-2, ADD-3 and ADD-4.
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