Proposed Title :
A 45nm CMOS Implementation of LECTOR based Shift Registers
Improvement of this Project:
Implement this LECTOR in 45nm CMOS Technology
Implement this LECTOR in D Flip flop
Using this LECTCOR NAND Gate and LECTOR DFF to implement 8-Bit Parallel In Parallel Output
Using this LECTOR NAND Gate and LECTOR DFF to implement 8-Bit Serial In Serial Output
- TANNER EDA
In this method of CMOS logic gate design a threshold voltage will take more complexity in leakage current and static power dissipation to reduced this complexity a proposed method will introduce a novel technique method with leakage control transistor it’s called LECTOR. A Proposed method of LECTOR will significantly reduced and cut down the leakage current without increasing dynamic power dissipation. In existing thing will introduce a two leakage control transistors P-TYPE and N-TYPE within the logic gate for which the gate terminal of each leakage control transistor (LCT) is controlled by the source of the other. In this proposed work of this paper presents to use this LECTOR to test the different digital circuits for future comfortable of LECTOR based digital circuits, here we are tested with LECTOR using D Flip Flops, LECTOR using 8-Bit Parallel in Parallel output method, LECTOR using 8-Bit Serial in parallel output method in 45nm CMOS Logic with using Tanner EDA Software. Finally proved the Power delay products terms for all those Circuits.
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LECTOR: A Technique for Leakage Reduction in CMOS Circuits
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