As CMOS technology growing towards nanometer scale, the performance of any electronics devices become challenging task because there are several parameter gets affected due to scaled down the devices, researchers have developed various types of logic circuits to increase the performance of a electronics systems. One of the most important categories of logic family which is required for design any types of electronics system is sequential logic circuits. D flip flops (DFF) are the most important basic building blocks of any digital very large scale integrated circuits (VLSI).The performance of DFFs directly affect the overall performance of the digital circuits. In order to obtain higher performances of the circuits, researchers have developed different types of DFFs. These structures can be divided into static and dynamic categories, however dynamic DFFs has better performance in terms of power delay product (PDP). D flip flops finds application in low power analog to digital converter (ADC) in different blocks of Multichannel ADC for PET scanner. Static D flip-flop is very slow when it has to be used in a MHz frequency range, so to avoid that, a TSPC D flip-flop in is selected. However there are numerous glitches in the intermediate nodes, due to that the overall performance of the circuit gets degraded.
Operation of the existing TSPC DFF
In the existing positive edge triggered TSPC D Flip-Flop in the Fig. 1, when the clock signal Clk is LOW, the input is isolated from the output Qb, since the node B pre-charged to HIGH, and Qb maintains its older value. When Clk is HIGH, node B will not be affected. Therefore when Clk is stable at either HIGH or LOW, the input is isolated from the output. When Clk makes a LOW-to-HIGH transition, the Qb will latch the complement of the input and Q will pass the input to the output. When the preset input (RESET) is LOW the preset PMOS will be ON and Qb maintains its value HIGH as long as RESET is LOW.Fig. 2 shows simulation results of the existing positive edge triggered TSPC D Flip-Flop and in this regard we were used CADENCE Virtuoso UMC 180 nm technology tool with clock frequency 1GHz and simulation times of 10 ns. The power consumed by TSPC D flip-flop is 75.43 µW.
- Very Slow Process in Static Design D FF
- Have More Glitches and nodes.
- Due to Positive and Negative Edge triggered TSPC D FF will have more Toggling.
- More Power Delay Product in Static D FF
In this paper we proposed a modified positive edge triggered TSPC D flip-flop (MTSPC DFF) which is some extended version of positive edge triggered TSPC D flip-flop. The modified TSPC DFF suspends the toggling of the intermediate glitches of nodes. As a result, the overall performance of the circuit is improved.
Operation of the proposed MTSPC DFF
Analysis of the behavior of node B reveals that for the times, when there is a path to ground, node B will always pre charged to HIGH when clock (Clk) is LOW and will return back to LOW when Clk is HIGH. So, whenever the input D is at a stable LOW for a long time with respect to Clk, node B experiences continuous toggling. Such unnecessary behavior not only accounts for large power consumption but is also a source of noise on the output node, Q, caused by erroneous glitches caused every time Clk makes a LOW-to-HIGH transition. To solve this problem, the proposed MTSPC DFF architecture reveals that whenever the path to ground is ON, pre-charging node B should be suspended to prevent toggling. A simple technique that works here is to add a PMOS transistor that prevents the pre-charging phase to occur without affecting the global operation of the flip-flop. To prove this claim, consider the following Fig. 3.
If Clk is LOW and D is LOW, node B, and consequently the node Qb, maintain their old values. If D changes to HIGH, node B pre-charge to HIGH; again, the output remains unaffected. Now, if Clk makes a LOW-to-HIGH transition, node B maintains its charge (HIGH), and the node Qb becomes LOW. After that, even if D becomes LOW again, the output will not be affected. If Clk makes a LOW-to-HIGH transition while D is LOW, node B will discharge, and the node Qb will be HIGH and Q will be low. Whenever the preset input (RESET) is low the preset PMOS will ON and the node Qb maintains HIGH. The simulation results of this preset-able MTSPC D flip-flop is shown Fig. 4 and in this regard we were used 45 nm CMOS technology tool with clock frequency 1GHz and simulation times of 10nS.The power consumed by MTSPC D flip-flop is 0.417 µW.
In order to evaluate the performance of the proposed positive edge triggered MTSPC DFF and positive edge triggered TSPC DFF, a 7-bit gray code counter is designed using both the DFFs.
Gray code counter has wide application in Electronics world, like low power counter based analog-to-digital converter (ADC). Synchronous Gray counter toggle a single bit at each rising edge of clock pulse and it is required to add feedback path from MSB (most significant bit) to LSB (least significant bit) coupled to feed-forward path from LSB to MSB in order to continue counting properly. These requirements lead to complex design methodology and low frequency of operation. An Asynchronous Gray counter was proposed to counter these problems. The gray code counter in Fig. 5 consists of two levels of Flip-Flops in toggle mode operation. The first level is asynchronous binary counter. Except MSB, outputs of first level counter goes to second level of toggle mode Flip-Flops. MSB bit of first level and outputs of second level build the Gray code. For high frequency gray-code counter implementation faster edge triggered Flip-Flops are needed. High frequency technique in CMOS is required in this context. A preset-able Modified True-single-phase positive triggered flip-flop (MTSPC) is designed and proposed for high speed Gray code counter. The proposed technique improves speed, noise and power issue in high frequency gray code counter.
- Dynamic D FF have more Speed and better in Power Delay Product
- Modified TSPC DFF suspends Glitches and nodes.
- MTSPC DFF will consumed less power and Maximum Frequency