Proposed Title :
A 45nm CMOS Technology Exploring low power and Fast 4 bit Full Adder using XOR/XNOR Gates
Improvement of this Project:
In this project we proposed 1 bit full adder using 45nm CMOS technology and compare with Existing 65nm CMOS technology.
- TANNER EDA
Proposed Abstract :
This paper, explores 4 bit full adder using XOR/XNOR or simultaneous XOR-XNOR gates and also consuming power and area of the circuit and increasing speed. This paper propose 4 bit full adder using full swing XOR/XNOR gates. The existing system simulated in 65nm CMOS technology and using hybrid 1 bit full adder. So it consumes more power for implementation. The proposed circuits simulation results based on 45nm CMOS technology model, it have superior speed and reducing area, power consumption and this circuit has high speed, low power using power delay product (PDP). In the proposed method, the numerical computation particle swarm optimization algorithm is used to achieve the desired value for optimum PDP with less iteration. In the proposed circuits new transistor sizing is implemented to optimize the PDP circuits. The proposed architecture results are compared with area, power and speed of the existing architecture.
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Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
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