Proposed Title :
A CMOS 130nm Implementation of Low Voltage Radiation Hardened 32-bit Memory module with using 13T SRAM Cell
Improvement of this project :
To Reduce the technology size to 130nm and power consumption
- Tanner EDA
In this paper, for the first time, a radiation tolerant bitcell, specifically designed for low-voltage operation, is proposed. The 13T dual-driven separated-feedback bitcell employs several novel techniques to achieve robust SEU suppression. Careful layout considerations were incorporated to further improve multiple-node strikes, while maintaining a unit cell size that is only 2×larger than a standard 6T static random access memory (SRAM) bitcell, implemented in the same 0.18-µm CMOS process. Extensive dynamic and static analyses were carried out to prove functionality and upset tolerance. Silicon measurements of a 32×32 (1 kb) memory macro show full functionality down to 300 mV.
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A Low-Voltage Radiation-Hardened 13T SRAM Bit cell for Ultralow Power Space Applications
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