Proposed Title :
Soft errors or single-event upsets (SEUs) caused by radiation strikes are the primary causes of failure in VLSI circuits operating within a highly radiating environment. Accordingly, maintaining data integrity in light of SEUs has become an integral aspect of memory cell design. Soft errors occur when an energetic particle hits and passes through a semiconductor material, potentially causing a bit flip in the memory cell. The energetic particle frees electron– hole (e–h) pairs along its path in the material as it loses energy. When the particle hits a reverse-biased p-n-junction, such as a transistor diffusion-bulk junction, the injected charge is transported by drift and causes a transient current pulse that changes the node voltage. Data loss occurs when the collected charge (Qcoll) exceeds the critical charge (Qcrit) that is stored in the sensitive node. The charge deposited by a particle strike can be calculated from the integral of the transient current pulse, and Qcrit is defined as the minimum charge deposited in a sensitive node that results in a memory bit flip. SEUs and other similar single-event effects (SEEs) are often considered when designing for space applications and other high-radiation environments. However, due to the reduction of Qcrit with technology scaling , SEUs can also occur in standard terrestrial environments at nonnegligible rates. Architectural solutions, such as error correction coding and triple modular redundancy (TMR), are often not effective for small arrays in ULP systems operated at low supply voltages, due to their high complexity and the resulting performance penalty. Technology solutions, such as silicon-on insulator and other process techniques, can improve the data reliability but do not entirely solve the SEE problems, and often high volume manufacturing is not feasible. Previously proposed bitcell solutions, such as the Dual Interlocked storage Cell (DICE), are designed for super threshold operation and fail when operated at low voltages.
Standard SRAM under SEUs:
SRAM blocks occupy the majority of the chip area and are the primary contributors to leakage power in many modern systems, including those intended for space applications. These trends lead to two major conclusions. First, due to their static power consumption, scaling the supply voltage of the SRAM macros is an efficient method to reduce total chip power. Second, the probability of a radiation strike on an SRAM bitcell is relatively high due to the large area that the SRAM core occupies. Therefore, SRAM soft-error mitigation has become essential for robust system design.
The conventional 6T SRAM memory cell, shown in Fig. 1, utilizes an active feedback loop between two cross-coupled inverters in order to retain its stored data value. This structure of the SRAM cell is very sensitive to SEUs, as any upset that causes one of the data nodes to cross the switching threshold of the adjacent inverter will result in a bit flip. When operating at low voltages, the switching threshold decreases, thereby increasing the soft-error susceptibility of the circuit.
- Power Consumption is high
In this paper, for the first time, a radiation tolerant bitcell, specifically designed for low-voltage operation, is proposed. The 13T dual-driven separated-feedback bitcell employs several novel techniques to achieve robust SEU suppression. Careful layout considerations were incorporated to further improve multiple-node strikes, while maintaining a unit cell size that is only 2×larger than a standard 6T static random access memory (SRAM) bitcell, implemented in the same 0.18-µm CMOS process. Extensive dynamic and static analyses were carried out to prove functionality and upset tolerance. Silicon measurements of a 32×32 (1 kb) memory macro show full functionality down to 300 mV.
Proposed 13t radiation tolerant bit cell:
SRAM design for low-voltage operation has become increasingly popular in the recent past. Various bitcell designs and architectural techniques have been proposed to enable operation deep into the subthreshold region. These designs generally incorporate the addition of a number of transistors into the bitcell topology, compared with the baseline 6T SRAM bitcell, trading off density with robust, low-voltage functionality. However, these bitcells were designed for operation under standard operating environments, and thereby, does not provide sufficient robustness to SEUs under high-radiation conditions. In addition, the design architecture of these cells is based on the standard 6T cell; therefore, the 6T cell has the same hardening ability to most, if not all, these unprotected cells.
The proposed bitcell is specifically designed to enable robust, low-voltage, ULP operation in space applications and other high-radiation environments. This is achieved by employing a dual-feedback, separated-feedback mechanism to overcome the increased vulnerability due to supply voltage scaling. The schematic representation of the proposed 13T bitcell is shown in Fig. 2. The storage mechanism of this circuit comprises five separate nodes: Q, QB1, QB2, A, and B, with the acute data value stored at Q. This node is driven by a pair of CMOS inverters made up of transistors N3, P3, N4, and P4 that are, respectively, driven by the inverted data level, stored at QB1 and QB2. QB1 and QB2 are, respectively, driven to VDD or GND through devices P1, P2, N1, and N2 that are controlled by the weak feedback nodes A and B that are connected to Q through a pair of complementary devices (P5 and N5) gated by QB2. By driving the acute data level by a pair of equipotentially driven, but independent, inverters, a strong, dual-driven feedback mechanism is applied with node separation for SEU protection.
Storage Mechanism (Hold):
The proposed 13T bitcell features two stable states, representing logic 1 and a logic 0, defined as the voltage level at node Q. The ON/ OFF states of the devices and the resulting voltage state at the internal nodes are shown in Fig. 3. Similar to a standard cross-coupled inverter structure, inverted voltage levels are held at the internal data nodes. Starting with the logic 1 state [Fig. 3(a)], the low level at QB2 enables Q to charge A to VDD through P5, thereby cutting off P1 and P2 and eliminating any pull-up currents to QB1 and QB2. Leakage currents from the strongly driven Q node through N5 charge node B, thereby turning ONN1 and N2 and enabling a discharge path to assist in holdingQB1 andQB2 at 0. Note that both nodes A and B are driven to a predetermined level during the write operation, as described below, and therefore are not reliant on the aforementioned leakage currents to set the initial storage level of the cell.
An almost symmetric process occurs in the logic 0 state, as shown in Fig. 3(b). In this case, QB2 is high, allowing B to discharge through N5 to Q and cutoff the pull-down paths from QB1 and QB2 through N1 and N2, respectively. Any charge stored at node A will leak through P5 to Q, enabling pull-up paths through P1 and P2 toQB1andQB2in order to replenish any charge lost at these nodes.
Standard SRAM topologies, such as the 6T bitcell, write data by driving the new level directly into the storage nodes, and therefore are required to overcome the circuit’s strong internal feedback. In contrast to this method, the proposed cell achieves writes by driving the weak feedback nodes (A and B), thereby removing much of the ratioed contention, inherent to direct access. A pair of write access transistors (N6 and N7) connects a unified write bit line (WBL) to nodes A and B. These devices are controlled by a write word line (WWL), such that when WWL is raised, A and Bare pulled toward the level driven upon WBL. This virtual connection between A and B creates inverters out of the transistor pairs of N1, P1 and N2, P2, drivingQB1andQB2to the opposite level of WBL. Accordingly, the written data level is driven back to Q through the dual-driven feedback inverters, bringing the cell to a stable state.
- Reduced Power Consumption in 32-bit Memory module
- Reduced Technology size 130nm-CMOS