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Time Interleaved SAR-ADC

A 6-GS/s 6-bit Time Interleaved SAR-ADC

₹8,000.00

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Source : TANNER EDA

Abstract:

This paper presents a 6-GS/s 6-bit time-interleaved successive approximation register (SAR) analog to digital converter (ADC) realized in 90-nm CMOS. The ADC consists of 32 single SAR-ADCs. The measured effective-number-of-bits (ENOB) at sampling rate of 6.144 GS/s are 5-bit at DC and 3.6-bit at the Nyquist frequency. The power consumption of the ADC-core without I/O’s and 4-to-1 output MUX is 359 mW for an input swing of 1 V peak to peak differential, resulting in a FOM of 4.9 pJ/conv. The proposed design of this Successive approximation register analog to digital converter in Tanner EDA at 65-nm technology and finally proved the comparison of area, power and delay.

List of the following  materials will be included with the Downloaded Backup:

1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)
2. Existing and Proposed Project Comparison
3. Architecture Diagram
4. Algorithm with Flow chart
5. Report for Phase1 and Phase2
6. Proposed abstract document
7. Reference materials
8. Literature survey with Reference Document
9. Online Support ( Team viewer/ Ammy Admin)

Proposed Title :

CMOS Implementation of Successive Approximation method of Time Interleaved ADC with 65nm technology

 

Proposed System:

  • In this Paper we are designed this work on 65nm CMOS Technology

Software implementation:

  • Tanner EDA

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A 6-GS/s 6-bit Time Interleaved SAR-ADC

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Time Interleaved SAR-ADC A 6-GS/s 6-bit Time Interleave...

₹8,000.00

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