Proposed Title :
CMOS Implementation of Successive Approximation method of Time Interleaved ADC with 65nm technology
A 6-GS/s 6-bit Time Interleaved SAR-ADC
High speed data converters with low to moderate resolutions are required for advanced applications such as UWB communication systems, storage systems and instruments. At the same time, the power consumption must be kept low. Interleaving successive approximation ADCs is an attractive way to realize a power-efficient high-speed ADC . However, no T&H circuits were realized in those ADCs. The sampling aperture mismatch between the single-ADCs becomes a large problem at high input frequencies. The ADC proposed in  using 160 SAR-ADCs to achieve 40-GS/s sampling rate. This ADC employs several complex foreground calibration techniques, which increase the chip area and the power consumption. This paper presents a 6-GS/s 6-bit time interleaved SAR-ADC in 90-nm CMOS with real time interface to allow real time operations and background calibration. The core area of the ADC is only 1.2 mm² and consumes 359 mW at 6.144 GS/s.
- More Power Consumption
This proposed work we are design this successive approximation ADC on 65nm size, with compared to 90-nm technology.
In the fastest changing electronics world, the grip which Analog electronics has always had, can never be changed or manipulated in any kind of applications right from old trivial designs to high end designs. In spite of the Herculean development in Digital electronics, the status of Analog electronics still remains proud enough as the real world always operates on Analog concepts. As all the real quantities are analog in nature, in any kind of applications there should be some means to convert those analog quantities into digital logic levels to process the signals according to the applications’ accuracy requirements. So the referred critical job of converting from Analog levels to Digital levels is generally carried out with the help of Data Converters.
The two obvious types of Data converters are Analog to Digital (ADC) and Digital to Analog (DAC) converters. In this thesis work, the type ADC is chosen to evaluate the merits and demerits with respect to its expected specifications. There again comes a major classification in this types of ADCs namely the Nyquist type ADCs and Oversampled ADCs mostly differentiated by the sampling frequency specified.
In all the portable applications, the main concerned issue would be the withstanding capacity of the battery power, which directly reflects to the power dissipation capability of all the circuits present in that system. As the technology develops/advances, the Digital world does as well, equally in terms of its circuits’ performance but the real bottleneck has been posed on Analog side of the application as low voltage analog powered systems demand some tough compromises in he circuit to maintain the same or improved performance levels as before. As normally any data converter circuits possess both analog and digital circuits in its system, the technological constraints like operating frequency, supply voltage levels, voltage swing limits, power consumption do speak a lot in terms of its difficulties in implementing the system in par to the advancement in technology.
SUCCESSIVE APPROXIMATION (SAR) CONVERTERS:
Among various advantages copyrighted to itself by its own architecture, the simple implementation is also a big plus for SAR converter. The whole system can be divided into four main subsystems namely.
- Sample (Track) and Hold Circuit
- Digital to Analog (DAC) Converter
- SAR Logic Block
The main operation of the SAR works on Binary search algorithm. The operation is assumed to have a digital value equal to half of the full -‐ scale value at the digital registers present in the SAR logic block. This condition leaves us with the logic 1 as MSB and rest of all the bits to be logic 0. The corresponding switches to this mentioned condition gets activated in the DAC block to have the necessary capacitors connected to the actual operation. This gives away the necessary voltage from the DAC block to the comparator input where this voltage level is compared with the input voltage. If the input voltage is less than the DAC voltage level, then the comparator outputs a logic 0 and logic 1 if it’s the other way around. This output value is stored in one of the SAR logic block’s registers and the next comparison is done in the comparator with the newly generated next DAC voltage level to get the correct digital level interpretation of the analog input voltage level. Usually the sampling frequency of the input signal is N (number of bits) times lesser than the clock frequency of the system clock as the internal clock has to be N times faster than the input clock to convert all the bits successfully. The capacitor stage in the DAC block have also got a dummy capacitor next to the LSB stage in order to make the total amount of capacitance to a power of 2 which makes the analysis better and sensible.
- Reduced the power level
- Reduced area
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A 6-GS/s 6-bit Time Interleaved SAR-ADC
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