We analyze problems on previously reported typical low-power FFs with comparison to a conventional FF shown in Fig. 1. Fig. 2 shows a typical circuit of differential sense-amplifier type FF (DiffFF) –. This type of circuit is very effective to amplify small-swing signals, so is generally used in output of memory circuits. In this FF, however, the effect of power reduction goes down in the condition of lower data activity, because these kinds of circuits have pre-charge operation in every clock-low state. Moreover, if we use reduced clock swing, a customized clock generator and an extra bias circuit are necessary.
Fig. 3 shows a circuit of conditional-clocking type FF (CCFF) –. This circuit is achieved from a functional point of view. The circuit monitors input data change in every clock cycle and disables the operation of internal clock if input data are not changed. By this operation, power is reduced when input data are not changed. But unfortunately, its cell area becomes almost double that of the conventional circuit shown in Fig. 1.
- Power consumption is high
After investigating many kinds of latch circuits, we have set up an unconventionally structured FF, shown in Fig. 4. This FF consists of different types of latches in the master and the slave parts. The slave-latch is a well-known Reset-Set (RS) type, but the master-latch is an asymmetrical single data-input type. The feature of this circuit is that it operates in single phase clock, and it has two sets of logically equivalent input AND logic, X1 and Y1, and X2 and Y2. Fig. 5 shows the transistor-level schematic of Fig. 4.
Fig. 7 shows simulation waveforms of the circuit shown in Fig. 6. In Fig. 6, when CP is low, the PMOS transistor connected to CP turns on and the master latch becomes the data input mode. Both VD1 and VD2 are pulled up to power-supply level, and the input data from D is stored in the master latch. When CP is high, the PMOS transistor connected to CP turns off, the NMOS transistor connected to CP turns on, and the slave latch becomes the data output mode. In this condition, the data in the master latch is transferred to the slave latch, and then outputted to Q. In this operation, all nodes are fully static and full-swing. The current from the power supply does not flow into the master and the slave latch simultaneously because the master latch and the slave latch become active alternately. Therefore, timing degradation is small on cell performance even though many transistors are shared with no increase in transistor size.
- Power consumption is reduced
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