## Description

**Existing System:**

After the first ever radio was invented in the late nineteenth century, there have been a multitude of changes in the radio technology. Conventional radios were designed to be fixed for a particular requirement and switching to a new standard of communication required to renew the radio design. The need for a flexible, adaptable technology led to the advent of the concept of Reconfigurable Radio Systems (RRS) around the twentieth century. The path to RRS is deemed to be achievable via two technologies namely Cognitive Radio (CR) and Software Defined Radio (SDR). In todays world, wireless communication is being employed for a vast variety of purposes, but the radio spectrum available is limited. SDR offers the solution to the problem with adaptive ways to share radio networks and frequencies among multiple services. This involves processing digital radio signal by means of software techniques. Thus the overall radio functionality is to be implemented in a generic hardware platform whereby there is a provision of reconfiguring the system in real time as and when required for multi standard implementation.

SDR is implemented by carrying out the signal processing at the transceiver end in digital domain instead of analog, thus digitization is done as close as possible to the antenna, while further processing is done using the software. For the system to be adaptable to various communication standards, the digital front end employs channelization of selective radio channels, which is done using a set of FIR filter banks and is a computationally intensive task. These channel filters have to operate at high speeds as they are placed right after the digital conversion block. Reconfigurable FIR filter architecture has been well documented in literature.

However most of these implementations fall short on implementing filter architecture that are feasible for SDRs with respect to optimized delay, low power consumption, and minimal usage of hardware resources. There has also been great interest in developing FIR filter architecture using residue number system (RNS) scheme. RNS is a technique of representing a binary number by computing its modulo division for a given moduli set [6]. The modulus must be relatively prime. Any number can be uniquely represented in the given dynamic range [0,M-1] and M is defined as in (1)

In the above equation the moduli set is defined as {????1, ????2, ????3…, ????????}, where ???? is the size of moduli set.

Most widely studied modulo sets employ ???????? as a power of two . Considering the value of q = 3, the possible moduli sets can be {2????−1, 2????, 2????+1} and {2????−1, 2????, 2????−1−1} . Several techniques are used for FIR filter implementation using RNS.

The potential for high speed arithmetic arises from the fact that operations on one value of calculated moduli residue can be carried out in parallel fashion, thus making this scheme modular and inherently parallel. Conventional FIR filter architecture based on RNS scheme employ forward converter (to convert the input binary number to RNS) , modulo multipliers and adders and finally a reverse converter (to obtain final output in binary form from RNS).

The idea of achieving reconfigurable filter architecture using RNS scheme is relatively new. However the problem of designing filter architecture for application in multi-standard wireless communication with RNS scheme is still not addressed. Wireless communication standards demand stringent adjacent channel attenuation specifications, for which very high order FIR filter architecture are required. Conventional filter implementation employ distinct FIR channel filters for each standard, and thus reconfigurabilty is achieved by switching to the current mode of operation.

In the author’s address the receiver problem by implementing a reconfigurable filter architecture that uses the LUT based approach. In this implementation a product encoder (PE) stores the residue result of multiplication and hence achieves hardware optimization. However this approach still requires the use of a forward converter for input values and the PE blocks need to be re-implemented when a different communication standard with a greater dynamic range is to be employed. There is also a significant limitation with respect to input wordlength.

In this paper, we propose two different ways to implement LUT based FIR filter that can be reconfigured as required, when the communication standard switches to a different standard which needs to satisfy an altogether different frequency response. As compared to, the proposed design uses minimal area with efficient use of hardware resources. The proposed architecture does away with the forward converter block for input values. The moduli set used is {2???? −1, 2????, 2????+1 −1} ,this moduli set offers two benefits, one is the increased dynamic range and the other is the capability to employ shift add approach which is not possible in the conventional moduli set {2???? − 1, 2????, 2???? + 1}. The two implementations proposed are designed in such a way that the increase in the number of combinations implemented by the encoder is reduced by a great order.

**Implementation Of Shift And Add Approach**

The conventional moduli set for q=3 is {2???? −1, 2????, 2???? + 1}. However, the moduli set chosen in this work is {2???? − 1, 2????, 2????+1 − 1} which facilitates multiplication by shift and add approach. The multiplication of a binary number X by 2???? can be achieved by a simple left shift operation by n times. Let the RNS representation of X be ⟨????1, ????2, ????3⟩ where ????1 = ∣????∣2????−1, ????2 = ∣????∣2???? and ????3 = ∣????∣2????+1−1. The modular multiplication of each modulus is discussed below.

**Multiplication for the Modulus 2****???? − 1****Multiplication for the Moduli 2****????****Multiplication for the Moduli 2****????+1 − 1**

**Disadvantages:**

- The Existing RNS FIR filter design uses maximum area.
- Efficient use of hardware resources is low.

**Proposed System:**

In signal processing, the system is to be adaptable to various communication standards, the digital front end employs channelization of selective radio channels, which is done using a set of FIR filter banks and it is a computationally intensive task. Residue number system is a technique of representing a binary number by computing its modulo division for a given moduli set. This paper proposes the new design concept of FIR filter design using the concept of RNS(Residue Number System) based on the LUT for reconfigurable applications. The adder approach offered by the chosen module set and the shift operation is the major advantages of the proposed RNS based FIR filter Design. This paper proposed the two different design implementation of LUT based RNS FIR filter. Type 1 is based on the concept of single stage of MA(Multiplicative Adder) and Type 2 is based on the multi stage MA(Multiplicative Adder). Thus, the two different proposed methods of RNS FIR filter is high efficient than the existing system of the RNS FIR filter design. Finally, The proposed two methods of LUT based RNS FIR filter design is implemented in the VERILOG and synthesized in the XILINX FPGA-S6LX9 and shown the comparison in terms of area, power and delay reports.

delay path for the transposed direct form is constituted by one multiplier and one adder. The RNS based approach, because of small sized residue operations and ability to perform parallel operations, provides an advantage. Also, use of coefficients multiplication results stored in a LUT gives added benefit. Further, this approach eliminates the requirement for a separate binary to RNS converter unit for the input X[n].

The proposed architecture implementations are shown in Figure. In the proposed approach the input X[n] is partitioned into two groups of 4 bits each, denoted as pair groups (PG). Thus there can be 16 possible PG combinations. All the individual blocks are similar in the two approaches but the order in which these blocks are placed differ. The section below summarizes the constituents :

**Modulo Product Encoder (MPE)**

The MPE block is implemented as an encoder for both implementation types and stores the possible combinations of multiplication of the input PG with the coefficient set in RNS with respect to the moduli set employed {2????−1, 2????, 2????+1−1}. It is clear that for the any moduli value ???????? , the residue can lie only in the range {0,????????-1} thus there exist ???????? possible values. The PG value of input and the coefficient is matched against the available combinations and the result corresponding to each moduli is selected. The selected result of MPE is in RNS, hence the need for a forward converter is avoided. Thus as it is shown in the diagram the MPE has two inputs one is a PG (4 bit) and the other input is coefficient value from the LUT Block. The number of combinations that the MPE implements is dependent on the moduli set employed. For example with k=5 the moduli set becomes {31,32,63} . Thus it stores {31×16},{32×16},{63×16} combinations for calculating the product of input with coefficient value. It its clear that with increasing value of k, the number of combinations increases as proportional to ???????? as compared to [16] where it increases as ????2 ???? thus reducing the area occupied by a factor of ????????.

**Modulo Structural Adder (MSA)**

In this stage the addition of the results from MPE takes place. The MSA stage accumulates the results at each tap. In a conventional modulo adder, the end around carry needs to be taken care of. However, in MSA this carry is propagated to the next stage. Thus only carry look ahead type adders are used instead of modulo adders in the proposed implementation.

**Multiplicative Adder (MA)**

This stage occurs right before the reverse converter. The MA block takes the pairwise values and uses the shift and add approach. The output of this stage is residue values corresponding to the final result.

**Reverse Converter**

The reverse converter for moduli set {2????−1, 2????, 2????+1−1},is implemented using the technique proposed. As is clear from the diagrams , In the first approach the MA is placed at last and the partial products are propagated till the last stage. While in the second design the MA stage occurs after each MPE.

**An Example**

In this section our proposed methodology of type I shown in Figure is illustrated with an example. Consider for k=5 the moduli set becomes {31,32,63} . As already discussed input X is partitioned into two PG’s. In this example input X is taken as 59=00111011. Let us denote

P G1 = 1011

P G2 = 0011

The decimal equivalents of ???? ????1 and ???? ????2 are 11 and 3 respectively. Now, consider a filter with coefficient ℎ1=65. The residues stored in LUT block of ℎ1 are{3, 1, 2}. The MPE stores the result of possible multiplication combinations of PG’s with ℎ1. The inputs to the MPE block are ???? ????1, ???? ????2 and {3, 1, 2} to calculate ???? ????1ℎ1 and ???? ????2ℎ1 respectively. The outputs of MPE stage are chosen according to ???? ????1 and ???? ????2 as:

P G1h1 = {2,11,22}

P G2h1 = {9,3,6}

Where ???? ????1ℎ1 and ???? ????2ℎ1 are the residue results of multiplication between ???? ???? and coefficient ℎ1. At the MSA stage , ???? ????1ℎ1 and ???? ????2ℎ1 will be added to the accumulated result from previous tap. However, in this example only one tap is considered, thus the accumulated outputs ????1 and ????2 are same as ???? ????1ℎ1 and ???? ????2ℎ1 .

z1 = p G1h1 = {2,11,22}………………….(12)

z2= p G2h1 = {9,3,6}…………..(13)

Now ????1 and ????2 are added as described in (14) and further the resultant will be given as an input to the reverse converter to calculate the filtered output Y[n].

z= z1 + z2 +z4 ………………….(14)

** Advantages:**

- More Security algorithm
- Less Area and less Power