## Description

**Existing System:**

Rapid single-flux-quantum (RSFQ) logic is considered to be the most well developed superconductor logic family in superconducting electronics. However, the static energy dissipated from the dc-bias current flowing through bias resistors eliminates the advantage of superconducting circuits when integrated to system scales. In an attempt to build more energy efficient circuits, adiabatic quantum-flux-parametron (AQFP) logic and other low power superconducting logic such as energy-efficient SFQ (eSFQ) logic, reciprocal quantum logic (RQL), LR-biased RSFQ logic, and low voltage RSFQ (LV-RSFQ) logic have been proposed and investigated by research groups around the world. Adiabatic quantum-flux-parametron (AQFP) logic is one kind of novel superconductor logic offering extremely high-energy efficiency for building high-performance computing systems. Being different from RSFQ logic, AQFP logic uses ac biasing/clocking, which eliminates the static power dissipation that dominates the total power consumption in traditional dc-power-based superconductor logic. In addition, the dynamic power consumption is considerably reduced by the adiabatic switching of the junctions. It has been demonstrated that the bit energy of AQFP logic can go below IcΦ0.

Currently, AQFP-based circuit design is verified by the simulation tool jsim at the analog level. The lack of a logic simulation environment is an obstacle for very-large-scale-integration (VLSI) circuit design of AQFP logic. Logic simulation of AQFP circuits is important for VLSI design, as it is much faster than low-level analog simulation. As the most dominant superconductor logic over the past decades, SFQ logic design benefited from the efforts of various research groups who developed HDL (hardware description language)-based digital simulation approaches specifically catered for it. SFQ input and output, both data and clock, are described as low-to-high-to-low pulses that last for 1 ps. However, in AQFP logic, waveforms are more complex because of the multi-phase clocking and the special encoding of the data. This suggests that a specific modeling approach should be used to describe the AQFP logic behavior. In this study, an HDL-based modeling approach for adiabatic superconductor logic simulation is developed, including a systematic approach for timing analysis.

**Disadvantages:**

- Low Efficiency
- High Area, power and Delay

**Proposed System:**

Adiabatic quantum-flux-parametron (AQFP) logic is one kind of novel superconductor logic offering extremely high-energy efficiency for building high-performance computing systems. This paper proposes the concept of Adiabatic quantum flux parametron logic simulation in (Hardware Description Language)HDL modeling approach. In this paper, the basic gates are implemented in the logic of Adiabatic Quantum Flux Parametron. By using this technique, this paper proposes the 16 bit carry look ahead adder which is implemented in the HDL modeling approach. Therefore, the AQFP logic based implementation of adder function has extremely high energy efficiency for high performance computing device when compared to basic CMOS Technology. Thus, the proposed system uses the AQFP based logic function of adder in order to attain better and high efficiency. Finally, this technique is implemented in the HDL and Synthesized using XILINX and compared the performance in terms of area, power and delay reports.

**1.1.1 Digital Simulation Approach For AQFP Logic**

**Top-down design flow**

Being similar to SFQ LSI design methodologies [8], [9], the typical design flow in AQFP VLSI circuits is to use the top-down design approach. Fig. 1 shows how the top-down approach works in this design: first, we focus on the big picture of the system in terms of function and scale, then we break down this big picture into the diagram design using a standard cell-based methodology. Back-end verification is executed by the HDL-simulator at the gate level to optimize the designed circuits and meet timing closure. A layout view will be generated after the system timing has been optimized.

**1.1.2 Gate-level modeling**

**Functional model**

One of the fundamental differences between semiconductor technology such as CMOS static logic and the superconductor AQFP technology is that CMOS is based on voltage-level logic whereas AQFP circuits operate on ac-power with gates activating during a specified period. Additionally, the AQFP convention for the representation of logic states requires that most of the logic components, including basic gates such as MAJORITY, AND, and OR, must be synchronous (clocked), i.e. combine logic function with storage capability. As a result, logic level simulation and timing verification of AQFP circuits with standard tools is possible only after the development of functional models for each AQFP gate, collectively forming a library that is invoked by an HDL simulator. This involves the use of HDL to specify the functionality and timing parameters of gates. We describe the functional behavior of an AQFP logic gate by combining a latch with Boolean logic, as shown in Fig. 2. The HDL code that represents this model is also given in this figure in a simplified form. By using this approach, we designed a cell library consisting of all basic AQFP logic gates.

The designed cell library [10] consists of basic logic gates AND, OR, NOT, MAJORITY, BUFFER and SPLITTER. Some of the logic gates are designed with normal input, inverted input, or combinations of both. It is easy to invert a normal input by negating the coupling coefficient of the output transformer of the logic gate without any other cost, which is an attractive feature of the AQFP logic family**Multi-value encoding approach**

An AQFP logic gate is driven by ac-power, which serves both as the excitation current and power supply (Fig. 3). Excitation fluxes are applied to the superconducting loops via inductors L1, L2, Lx1 and Lx2 using an excitation current Ix. Then one single flux quantum is either stored in the left or right loop, depending on the direction of the input current Iin. As a result, the logic state can be represented by the direction of the output current Iout. The positive current is encoded as logic ‘1’, whereas the negative current represents logic ‘0’.

**Interconnection ****modeling**

Unlike in CMOS VLSI design, interconnect wires serving as clock-power bias and data transmissions are built at the cell-level and are described as bidirectional transmission lines with parameterized delay information in terms of seconds per unit length (typically ps/µm). This is an essential part in analyzing timing variation between certain logic elements. The delay is modeled as a transport delay in HDL.

**Timing mapping**

Although excitation currents serve as clocks and synchronize the AQFP logic gates, timing issues still exist due to clock skews and signal delay, especially when the circuit scale becomes large. Fig. 5 shows the example waveforms of malfunction due to a clock skew of 12 ps in an AQFP circuit consisting of buffers in series. One can see that incorrect output occurs when the excitation current is delayed by a certain period, which means a timing window exists between input current (input) and excitation current (clock).

We define this timing window as a certain period in which the input (din) must arrive relative to the clock (xin), shown in Fig. 6. Variables ‘clock-’ and ‘clock+’ are used to represent the left and right edge of the mentioned timing window. The origin of the window represents the ideal clock propagation (zero clock skew). Fig. 7 (a) shows the flow chart of how the timing window is verified at the gate level. A finite-state machine (FSM) is also adopted to further ensure the valid input order as illustrated in Fig. 7 (b).

Fig. 8 shows an example of simulated waveforms of several cases with different timing variations. The first two outputs are correctly driven by the synchronized excitation current, whereas the following outputs are indicated as unclear states represented by the HDL state ‘x’, corresponding to invalid data-clock input timings.

**Parameterizable**

approach Since the timing window between the input current and excitation current may have a strong dependence on the shape of excitation current (sinusoidal, trapezoidal), clock operation mode (3-phase, 4-phase), clock amplitude, and operation frequency, our HDL-based models are designed in a parameterized approach. It has different sets of timing parameters, corresponding to different clock/excitation phase mode (3-phase mode is widely used now), different operational frequency and even different fabrication technologies.

The typical flow chart of running an AQFP digital simulation is presented in Fig. 9. At the top-level, testbench.v incorporates information such as the circuit function, input/output ports, fabrication process, excitation current amplitude, operation frequency, and clock operation mode. Various test patterns that are used to drive the circuit under test are written in stimulus.v along with appropriate top-level auto-checking routines to verify functionality. Circuit net lists are automatically generated for the gate-level simulation. The functional behavior of logic gates is described in gate.v, where ‘gate’ is the name of any gate existing in the library. And in parameters.v, cell information such as the timing window, junction count, cell area and energy are defined as a table with flexibility corresponding to the top-level variables (process, excitation current variation, clock operation mode, etc.) Before simulation, this parameter table will be loaded first to match the current top-level variables. For instance, the simulation will be initialized with parameters to describe a design that uses the standard process with 70% of normal excitation current and driven by 3-phase clocking. This information provides the key to the look-up table to obtain the appropriate gate-level parameters for each instanced gate in the design.

Energy efficiency is one of the most important metrics of advancement in modern computer design because power consumption is a serious limitation to realizing future supercomputers.1–3 Therefore, recent progress in the energy efficiency of superconductor logic has attracted a great deal of attention in the development of energy-efficient superconductor computing systems.4,5 With a focus on reducing the static power consumption in rapid single-flux-quantum (RSFQ) logic,6 energy-efficient superconductor logics7–9 have achieved a bit energy less than or equal to 1 aJ. Moreover, 8-bit adders using reciprocal-quantum-logic (RQL) and energy-efficient RSFQ (ERSFQ) logic, the energy dissipations of which were only 82 and 320 aJ per clock cycle, respectively, have been experimentally demonstrated.10,11 These low energy dissipations reveal the high energy efficiency of superconductor logics in comparison with semiconductor digital circuits.

Adiabatic quantum-flux-parametron (AQFP)12,13 logic is an energy-efficient superconductor logic, in which both dynamic and static power consumption are significantly reduced due to adiabatic switching operations. The energy dissipated during a switching event is proportional to the operation frequencies and inversely proportional to Q of Josephson junctions,14 which indicates that there is no minimum energy bound in adiabatic switching operations in AQFP logic. Moreover, we have demonstrated reversible computing using logically and physically reversible AQFP gates with high-Q Josephson junctions15,16 and have estimated that the energy delay product can approach the quantum limit given by h/2.1.

** Advantages:**

- Extremely high efficiency
- Low Area, Power and Delay

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