Existing System:THE main task of a ternary content addressable memory (TCAM) is to search contents stored in its memory. This is done by accessing stored data by content rather than by address; this is unlike static random access memory (SRAM), which accesses content using the address. TCAM compares the search query with the contents that are preloaded in the entire memory array simultaneously and generates the result. TCAM can be used in one of the three states, as follows: two binary states (0 and 1) and a do not care state (X). Binary states are stored in data cells, and they do not care state is stored in mask cells
A typical TCAM has the advantage of fast searching over SRAM-based searching solutions, but it also has drawbacks. A TCAM cell uses more transistors than an SRAM cell. Hence, it has high production cost per bit of memory storage and exhibits less storage efficiency than SRAM devices of comparable bit density and access time. This drawback is mainly because of emulating the do not care state, which requires additional hardware memory resources in terms of bits used for the emulation . To overcome the drawbacks in a typical TCAM, such as relatively high energy consumption , complex memory structure, limited storage density, low scalability, heavy licensing, and royalty.
The SRAM-based TCAM memory architectures generally require SRAMs to map TCAM bits. The search operation requires a fixed length binary query string (QS) as the address to access the SRAM. It generates the vector that contains information about matched address locations. The logical 1s and 0s in the vector are treated as matched and mismatched address locations, respectively. Later, a priority encoder is used to prioritize the locations of the vector when multiple matching bits are present in the vector.
SRAM has an inherent hardware structure suited to store data, which are accessed in a sequential manner. The SRAM-bit utilization in the SRAM-based TCAM can be negatively affected during the mapping of TCAM bits that are simultaneously accessed. The decrease in the memory utilization efficiency of SRAM can be even more significant for large TCAM emulations. This brief focuses on efficiently using resources, such as memory and throughput, and proposes a resource-efficient SRAM-based TCAM (REST) emulation architecture to make use of memory–throughput tradeoff in SRAM-based TCAM.
- More Area size
- More time for reading and writing operation
- More time to find the CAM
The implementation of Proposed system of SRAM-based TCAM is to search contents stored in the memory. This is done by accessing stored data by content rather than by address; this is unlike static random access memory(SRAM), which accesses content using the address, here we are modified the SRAM of single ported to Multi ported, so it will search the contents stored in the memory using multi port. The utilization of block or Distributed RAM is critical performance factor for multi-ported memory design on field programmable gate array (FPGA), this paper introduced a new perspective and more efficient way of using a conventional memory of Multi input and Multi output port based upon TCAN memory size.
Field Programmable gate array, have been broadly used in fast prototyping of complex digital systems. FPGA contain programmable logic, arrays, usually referred to a slices. Slices can be configured in to different logic functions. The flexible routing channel can support data transferring between logic slices. In addition to implementing logic operations, if needed the slices can also be used as storage elements, such as flip flops, registers, or other memory modules. In this same way via the TCAM signal ported memory will be modified to Multi ported memory, with reduced the slice configuration in FPGA. The modified architecture of Resource efficient multi ported SRAM based TCAM is shown in below architecture.
- Less Area size compared to existing system
- Less time for reading and writing operation
- Less time to find the CAM