| Proposed Title :|
Low Power CMOS 130nm Glitch Energy Reduction and SFDR Enhancement Techniques with Binary Weighted Current Steering DACProposed System:
Glitch is an important measure in the output signal quality. When the binary-weighted current-steering DAC operates at a high sampling rate, glitch caused by the transitions of current switches will have significant impact on the output signal. In the DACs used for video display systems, excessive glitch can cause color shifts at the borders of objects resulting in sparkles on the screen. Moreover, the spurious free dynamic range (SFDR) is quickly reduced with the increasing amplitude of the glitches. The largest glitch is usually generated during major carry transitions, because all the bits are switched and timing skews exist among different current switches, as shown in Fig. 1. The metric of glitch is glitch energy (or glitch area), which is defined by the time integral of the analog output of the glitch transient. The output glitch can arise from the following two mechanisms: 1) the first one is capacitive feedthrough in the current switch from switch driver and charge injection in the switch, where this glitch can be improved by shrinking the size of the switch or series of a buffer between output and switch and 2) the second one is the difference among the switching time for different bits in a binaryweighted DAC, where this effect could be modeled as cell-dependent delay differences. Although the deglitching circuits, such as quad-switching and return-to-zero (RZ), can help to remove the transient glitch, the major drawback of quad-switching is the increased dynamic power consumption and complexity driven from the extra switches and control signals, while RZ data streams are not acceptable for many applications. Recently, some dynamic element matching techniques were proposed to reduce the mismatches of current sources and glitch energy. However, the decision logic circuit is often complex and also increases noise floor, distortions, and digital power consumption.
- High noise
- High power consumption
Proposed System:A 10-bit 400-MHz binary-weighted DAC is presented with a linear-weighted number of buffers and retiming latches. The compensation capacitance was added to reduce the glitches due to the timing skew of retiming latches, where the overhead for area and power is very small. Besides, a layout scheme for SFDR enhancement is also included.
The input buffers were implemented by inverter-based buffers with a Schmitt trigger function, which can filter out transient noises from signal source or coupling noises from printed circuit board. D is a retiming latch, which is realized by the clock-gated SR latch. The clock circuitry is the highest speed element in the DAC, so to decrease digital power and area, the number of latches and buffers used is linear scaled, not binary weighted. In this design, only one latch and buffer is used for bit 0∼bit 7 individually, two latches and buffers are used for bit 8, and four latches and buffers are used for MSB due to the increase in the loading. The total number of latches is 14, which is much less than 1023 (binary weighted or unary), where this arrangement is designed by the simulation of dynamic capacitance of current switches and glitch simulation. More about these simulations will be addressed in the next section III. S0–S9_4 are the inputs of current switches. Si drives 2 I units of current source and current switch (CSCW), where i =0–7. S8_1, S8_2, S9_1, S9_2, S9_3, and S_4 also drive 128 CSCW. The CSCW cell combines current switch and current source as a unit in both schematic and layout to minimize the parasitic capacitance at node X, as shown in Fig. 2, as it will affect the SFDR, performance seriously. The dynamic capacitance compensation circuit is added between retiming latches and current switches to reduce the timing skews caused by different loads of retiming latches for different bits. The total area of the dynamic capacitance compensation circuit is very compact compared with traditional input buffers and latches.
- Power consumption is low
- Low Noise
- Tanner EDA