Proposed Title :
FPGA Implementation of Novelty based High Performance and Low Power 8-Bit, 16-Bit, 32-Bit, 64-Bit and 128-Bit CRC Implementation
Improvement of this Project:
To design a novelty based CRC Implementation using Shifting and XOR’ed technique and proved the performance of area, delay and power.
Implementing CRC Generation and CRC Checking at 8-Bit, 16-Bit, 32-Bit, 64-Bit data width.
Cyclic Redundancy Check is a well know error detecting code that is commonly used in Ethernet, PCIe, and other transmission protocols. In high performance environments of current FPGA based implementation solution encounter the problem of excessive resource utilization in high performance scenarios. In this proposed method to reduce a zeros passing problem in this existing cyclic redundancy check and introduce a shifting and XORed based technique with polynomial security codes, it will increases more security and critical path delay in all signal transmission applications. Thus, the proposed cyclic redundancy implementation to prove the higher resource utilization in multiple data width of 8-Bit, 16-Bit, 32-Bit, 64-Bit and 128-Bit. Finally this work was developed in verilog HDL and synthesized in Xilinx Vertex-5 FPGA and proved all the performance of area, delay and power.
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Low-Cost and Programmable CRC Implementation Based on FPGA
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