Proposed Title :
FPGA Implementation of Comparative Analysis of 128-Bit Advance Encryption Standard and 128-Bit Advance Decryption Standard using 32-bit Memory Block
Improvement of this Project:
To design a Advance Encryption Standard and Advance Decryption Standard at 128 Data Width using 32-bit Memory Block and proved the comparisons in Zynq 7000 FPGA using Xilinx VIVADO.
- Altera Quartus & Xilinx
In a recent information security based application will challenging also growing constantly due to technology improvement. The hackers take advantages of the latest sophisticated equipment and technology also breaking down on every safety devices. Therefore, recent information security are increasingly dependent on information protection, either software or hardware implementation to ensure data privacy. This proposed work uses a hardware implementation of field programmable gate array unit, which has less complexity, more flexible and provides more energy efficiency. The emphasis of this work is on the hardware implementation of the Advance Encryption Standard (AES) as a cryptographic algorithms. The proposed algorithm will developed a comparative analysis of 128-Bit data width using 32-bit memory block, and also implemented with encryption and decryption standard. This proposed algorithm will developed in Zynq 7000 FPGA using Xilinx Vivado and compared all the parameters.
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A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm on FPGA
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