Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption
Baseband OFDM for multi-carrier transceiver is increasingly being used by the modern digital mobile communication systems. OFDM is having high spectral efficiency because it uses the idea of elimination of guard bands and use of the overlapping but orthogonal subcarriers. We are dividing high rate data stream is into a number of low rate data streams that are transmitted over a number of multiplexed orthogonal subcarriers. The low rate data streams allow us to add sufficient guard time between two symbols which was very small in high rate data stream. This helps us in enabling the system to perform well in dispersive channel which causes the symbols to spread in time and interfere with each other this phenomenon is called as „Inter symbol interference (ISI)’. OFDM can be viewed as combination of a modulation and multiplexing technique, and its hierarchy lies in the physical and medium access layer. A basic OFDM transceiver consists of a QAM or PSK modulator/demodulator (depending on spectral efficiency), a serial to parallel/parallel to serial converter, and an IFFT/FFT module. The block diagram of basic OFDM system is shown in Fig 1. The transmitter has an input bit stream, serial to parallel converter, constellation mapping, IFFT, Digital to Analog Converter. The receiver has an Analog to Digital Converter, FFT, parallel to serial converter, demodulation, and output bit stream.
Implementation of transmitter and receiver is done independently and tested it on FPGA, and then both the subsystems were merged to form one system. We designed the system for two sets of subcarriers one is using 4 subcarriers and the other using 8 subcarriers. Design flow for both the system is same. It is explained as follows. Before designing the system we started with the understanding of the block diagram. It gave the idea about operations which are needed to be performed on FPGA. Then we developed the algorithm for sequential and concurrent operations. To make the design more parallel, the operations are broken in to processes and independently written in VHDL. The system is designed completely on Xilinx Project Navigator using VHDL coding as design entry method. Then the system is simulated on ISE simulator for timing analysis. Finally the design is synthesized on FPGA Spartan 3e device using high level synthesis tool.
Transmitter Design Flow:
16 bit long input data stream is stored in an array using VHDL. Simultaneously, serial to parallel conversion is done in independent process along with mapping of the parallel, grouped bits in to complex constellation for QPSK. Real and imaginary parts of constellation points are stored two different arrays. Look up table is utilized for mapping of grouped bits in to constellation points. Complex multiplications are needed to be performed for 8 point IFFT calculations. Twiddle factors are stored in array, which are necessarily floating point. An algorithm is developed for the floating point complex multiplications. IFFT processor is multistate process which uses different IP cores for predefined operations. Two separate systems are designed using 4 subcarriers and 8 subcarriers. To have different number of subcarriers means changing the number of points in IFFT processor. A separate process maps the real and imaginary values in the range of DAC and transmits them through separate channels. DAC used for this purpose is LTC 2624 which is interfaced with FPGA through SPI communication. For transmitting particular OFDM symbol through DAC it must be converted in the format that is acceptable by DAC. Then this control word is transmitted serially to DAC with control signals to start the conversion.
Receiver Design Flow:
Design of receiver is done separately before connecting it to transmitter. FFT is calculated using same algorithm which is developed for transmitter. DIT radix-2 butterfly is used to calculate FFT and IFFT. Xilinx Project Navigator and VHDL coding is used to design the receiver. Similar to transmitter, floating point complex multiplication, additions and subtractions in receiver are done using the IP cores. Operations of receiver are broken in to different processes and merged to have complete system. After FFT operation, demodulation is done by using look up table approach. The reception is completed once the bits are recovered from the received constellation. Separate receivers are designed and tested for 4 points and 8 points transmitter. ISE simulator is used once the design code is ready for timing analysis and then code is synthesized on kit.
- Less Number of Arithmetic Operations
- Less Efficiency
- More, area, power and more delay
Proposed System :
In a recent technology of digital communication system where as multiple carriers signal are used to transmit and received the data in the application of Orthogonal frequency division Multiplexing (OFDM). In a OFDM method of digital signal processing application will not support large integers values in all arithmetic operations. Here, we introduce a Fully Homomorphic encryption(FHE) algorithm to allows a computations in large integer multiplication, addition and division to be carried out directly on cipher texts for ensuring data privacy on un-trusted servers, thus attracting much attention for cloud computing applications. In this paper, we are focusing on the design and implementation on OFDM with using Large integer multiplication with using NTT (Number theoretic transform) and INTT(Inverse Number Theoretic transform) in Fig.2 will shown the basic diagram of complete OFDM Design with using NTT/INTT method. This FHE method will have various efficient schemes to tackle and carrying out large integer multiplication based on Schönhage – Strassen algorithm (SSA). This proposed method will designed in VHDL and synthesized in Xilinx FPGA-S6LX9, finally compared with existing OFDM Technique of FFT and IFFT Method and shown the compared terms of Area, Power and delay.
Schönhage – Strassen Algorithm:
The SSA is an NTT-based solution for carrying out large integer multiplication. As shown in the SSA algorithm, let X and Y represent the u-bit integer multiplicand and multiplier, respectively, and the two operands are partitioned into M digits using base B, where M = u/b and B = 2b. Moreover, zero padding is needed to extend both operands to 2M digits before performing cyclic convolution. The convolution is accomplished by doing NTT, point-wise multiplication, and INTT sequentially. The final result Z is then obtained by resolving carries on the INTT output according to the base B. NTT can be viewed as a discrete Fourier transform defined over finite field Zp . An N-point NTT is defined as
where 0 ≤ k < N −1 and WN is a primitive Nth root of unity in Zp.
Operand Reduction Scheme for Butterfly Unit:
As can be observed from, the summation of the r 192-bit operands x n s multiplied by the associated twiddle factors for a radix-r BU can be interpreted as the summation of the left circular shift of xn by n · k · t (mod 192) bits. For instance, Fig. 1 illustrates the relationship among the left circular shift of xn s for computing X1 by a radix-r BU. Given the r operands (OPs), a direct implementation of the summation operation using a carry-save adder (CSA) tree will take at least log1.5 (r/2) levels, which leads to a large area requirement for large r. The result is then reduced to 64 bits by performing the 192-bit modulo-p operation.
Since there are 128 bits of zeros in each operand, we can take advantage of the zero elements by merging compatible operands to reduce the number of effective operands. This in turn might reduce the level of the CSA tree. In this paper, the two operands OPi and OP j are said to be compatible if the positions of their constituent data points xi and x j do not overlap, such as OP2 and OPr−1 in Fig. 1, and they can be combined to yield a new operand. Note that for each Xk , 0 ≤ k ≤ r − 1, the set of its corresponding operands derived from the left circular shift of xn is determined by the indices n and k.
Given a radix-r BU, this paper explores the inherent features in the set of operands for each Xk and proposes an efficient operand reduction algorithm to minimize the number of effective operands. Moreover, to increase the chance of merging operands, we extended the concept of compatible operands to consider the segmented data point xn described below. Applying the proposed schemes can reduce the number of operands by at least r/2 in each summation operation of Xk , 1 ≤ k ≤ r − 1, and retain r reduced-length operands for X0.
Block diagram of QPSK Modulator:
As shown in Fig.3, of QPSK Modulation, here the input will provided as a Binary information, and its converted into 2Bit serial to parallel form, then the 2Bit form will provided to voltage control oscillator scheme of COS and SIN signal generator with Encode TX pulse, and its multiplied to carrier frequency then the signal to be added before transmission output. The QPSK modulation is determined a format of phase changes from previous signal. In the Quadrature modulation will have four possible states such a Hence this each states which is represents two information bits, it splitting of binary patterns as same of QPSK modulation technique, it shifter the phase to about depending upon the requirement.
In the Modulation of wireless communication technology will used to transfer the data by changing the frequency, amplitude and phase of the carrier signals, with this digital data of modulation scheme it will need to map the corresponding signals for example in the binary modulation ‘0’ and ‘1’ will be map to the time(t) of waveforms. In modulation each input data will form a group of bits to the form of M=2b which is corresponding to M-ary modulation for M>2. The Quadrature Phase shift keying is also one of the modulation technique of M-ary modulation M=4, with this M will denoted as symbol of four distinct waveforms of different phase. The QPSK Modulation will achieve the same bandwidth, data throughput, bit error rate, power efficiency with compare to the QPSK. Four symbols of M=4 is located with equal spacing.
Block diagram of QPSK Demodulator:
As shown in Fig.6, the input signal of modulation will received to BPF(Band Pass Filter), it will reduce the noise in upper and lower range of input signal, and the signal will pass through carrier recover circuit, such as the numerical control oscillator will take to correct the error signal and generate the high frequency noise using COS and SIN multiplier, after multiplier the output signal will given to low pass filter(LPF), and we get the noise reduction output, it will given as a input of decision circuit, the decision circuit will find the range of frequency changes as per the modulation and generate the differential signal, those differential output will multiplexed and taken as a output in recovered signal.</p?
- Large Number of Arithmetic Operations
- More Efficiency
- More Area, Delay and Power
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Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption
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