Proposed Title :
FPGA Implementation of High Performance FIR filter design with using Distributed Arithmetic based Approximate Sum of Products.
Improvement of this Project:
To design 16-Tap FIR Filter design using a method of Approximate circuit in ASOP1, ASOP2, ASOP3, finally compared with this ASOP’s to shown the FIR Filter performance in terms of Area, delay and power.
- Modelsim & Xilinx
In a recent research of Approximate computing will provide a long lost bit error rate and also provide a power efficient with less area in digital signal processing applications. In a key component of arithmetic operations, a SOP (Sum of Product) method will have priority in approximate implementations such as calculation of inner products between vector based arithmetic operations. Here a arithmetic operation of approximate sum of product (ASOP) method will designed in three type of method in SOP Structure of K=3, N=16, these method will support without using multiplier design, such as 1) Generic method of ASOP1, 2) Priority encoder method of ASOP2, 3) Multi-Operation with truncated 18-m bits method of ASOP3. In this proposed work of this paper will implement this ASOP1, ASOP2, ASOP3 with using FIR Filter design, and shown the performance with this three method, and finally design this logic on VHDL and implemented with Xilinx FPGA-S6lx9, and shown the performance in terms of area, delay and power.
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Approximate Sum-of-Products Design Based on Distributed Arithmetic
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