Proposed Title :
FPGA Implementation of High Complexity method of Multiple Cell upsets in (15,7) BCH Codes in Space Applications.
Improvement of this Project:
To design Error Correction Codes for Multiple Cell Upsets in a method of BCH (15,7) Code with Syndrome Calculation of Multiple Error Correction and also compared with existing Hamming Code.
- Modelsim & Xilinx
In a recent technology of Digital Signal Processing based application method will have number of errors will occur with integrated SRAM memory on during signal transmission and reception it will reliable with conventional fault tolerance technique with probability of occurrence in single-cell upsets and multiple cell upsets. In a existing thing will have a Hamming code will also present parity checks in bi-dimensional layout method to correct and detect the errors. The main drawback of the Hamming code can detect only one bit in error can be corrected and also detect some double error patterns, in addition to the SEC. In this paper presents this method on BCH Codes with Multiple Cell upsets, in this BCH Code can capable to detect and correct a Multiple Fault Error Corrections, and it will use variant check matrices to extend ideas from Hamming and Reed-Solomon Codes, with detect many errors. In this method to implement in VHDL and synthesized in Xilinx FPGA-S6LX9, finally compared with Hamming and BCH codes based Multiple-Cell Upsets of error correction and shown in the terms of area, delay and power.
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Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications
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