FPGA based BSTX FIR Filter Design using Truncation Multiplier
To Design the FIR Filter with the five blocks of FIR8, FIR8FirstI, FIR8FirstQ, FIR8Last and IntCompMux based on the FPGA concept using Truncation Multiplier
- Modelsim & Xilinx 14.2
With the widespread use of the high-speed digital signal processing(DSP) technology, FPGA has also increased speed and integration, which provides a new way for digital signal processing. FIR(Finite Impulse Response) Filter is the basic component in the digital signal processing system, whose impulse response is of finite duration, because it settles to zero in finite time. This paper proposes the new design concept of FIR Filter based on FPGA. This includes five blocks of operations are FIR8, FIR8FirstI, FIR8FirstQ, FIR8Last, IntCompMux. Thus, the FIR Filter Design based on FPGA has the greater advantage. Because, FPGA architecture of LUT’s is be applicable to implement real-time, high speed and reliable FIR filter. Therefore, this paper focused on the Fir filter which is based on concept of FPGA. Finally, the proposed FIR filter based on FPGA is implemented in the VHDL and synthesized in the XILINX and compared in terms of area, power and delay reports.
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FIR Filter Design based on FPGA
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