Proposed Title :
FPGA Implementation of M-PSK Modulation and Demodulation of 4, 8, 16-QPSK
The digital modulation techniques have gained more importance compared with analogue ones in the recent years because of many advantages such as better noise performance, greater security and easier implementations in very large scale integrated circuits (VLSI). For satellite communications, M-PSK (phase shift keying) digital modulation schemes are increasingly used as they are more bandwidth efficient, power efficient and have a reasonable receiver complexity. In M-PSK scheme, the modulation is done by varying phase of the carrier for a corresponding input symbol. All the architectures of the quadrature phase shift keying (QPSK) modulator in the literature consist of multipliers, which occupies large area, contributes to a large critical path delay on a VLSI chip and eventually decreases the speed of operation. The novelty of the proposed modulators is that they do not require any multipliers and hence they provide high performance in terms of speed and area. The proposed QPSK modulator and demodulator form the fundamental component in designing architectures for 8PSK and 16PSK systems. In the authors had presented a multiplier less architecture for offset-QPSK modulator which uses a CORDIC module. The modulators based on CORDIC offer better phase resolution but the hardware complexity is more compared with the modulators implemented using look up table (LUT) approach. This paper presents all the architectures based on LUT approach as this approach requires much lesser hardware without compromising in higher speeds of operation. Based on a demodulation algorithm presented in for 32-APSK system, this paper proposes new algorithms for 8PSK and 16PSK systems which can be implemented both in analogue and digital domains.
- More Area and power
- Low Performance
In the Proposed system of PSK Modulation and Demodulation will integrated with 4PSK, 8PSK and 16PSK in single architecture, with reduced the High complexity and reduced power consumption. Here, the input data to be transferred as a Image file, this image will loaded into MATLAB to convert Image to hex conversion, these hex file data will written into Memory with help of Test bench, and transferred after filling the image data. Once data is started, it will process on LSB Shifting of data byte based configuration will decide quadrant phase shifting of sine and cosine signals in modulation scheme. In demodulation scheme, to receive quadrant modulation and analysis sine and cosine signal phase shifting, using demodulator oscillator and provide a output data. Finally the design will tested with fading channel based noise generation with BER Testing.
- Less Area and Power
- High Performance