Description
| Proposed Title : Low Power and High Speed Area Efficient Highly Reliable Frequency Multiplier for DLL-Based Clock GeneratorProposed System:
Software implementation:
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Existing System:
In the existing system to design the frequency multiplier with sequential pulse generator and generate the multiphase clocks using DLL core. Based on the sequential circuit, the pulse generator is generating the delay based clocks for the frequency multipliers. The previous design of the frequency multiplier is given below.
Disadvantages:
- Low Speed with more delay
Proposed System:
The proposed DLL-based clock generator is composed of a DLL core and the proposed frequency multiplier, as shown in Fig. 2. To enhance the lock time, which is an important design parameter in the clock generator, a dual-edge-triggered phase-detector-based DLL core is adopted. Similar to previous frequency multipliers, the proposed frequency multiplier is also composed of a pulse generator, multiplication-ratio control logic, and an edge combiner.
To solve the speed and the reliability issues of previous edge combiners, an HSHR-EC, which consists of a precombining stage, overlap canceller, and push–pull stage, as shown in Fig. 3, is proposed. The two-step edge combiner, precombining, and push–pull stage are used to enhance the maximum multiplied clock frequency. The overlap canceller is used to guarantee the stable operation of the frequency multiplier.
Advantages:
- Increases the speed and reduced the delay
Software implementation:
- TANNER
