Name: High Speed Low Power and Highly Reliable Frequency Multiplier for DLL Based Clock Generator
SKU: 6440
Price: 8000.00 INR
Availability: InStock

High Speed Low Power and Highly Reliable Frequency Multiplier for DLL Based Clock Generator

~~₹12,000.00~~ ₹8,000.00

Click here to Download Abstract Document

Source : TANNER

Abstract:

To propose a novel frequency multiplier with high-speed, low-power, and highly reliable design for a delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. In addition, by applying the logical effort to the pulse generator and multiplication-ratio control logic design, the proposed frequency multiplier minimizes the delay difference between positive- and negative-edge generation paths, which causes a deterministic jitter. Finally, a numerical analysis is performed to analyze and compare the performance of the proposed frequency multiplier with that of previous frequency multipliers. The proposed frequency multiplier is fabricated using a 0.13-µm CMOS process technology, and has the multiplication ratios of 1, 2, 4, 8, and 16, and an output range of 50 MHz–3.3 GHz. The frequency multiplier achieves power consumption is 17.49mW. The proposed architecture of this paper is analysis the logic size, area and power consumption using tanner tool.

List of the following materials will be included with the Downloaded Backup:

1. Source code ( Modelsim/ Xilinx/ Quartus/ DSCH3/ Microwind)

2. Existing and Proposed Project Comparison

3. Architecture Diagram

4. Algorithm with Flow chart

5. Report for Phase1 and Phase2

6. Proposed abstract document

7. Reference materials

8. Literature survey with Reference Document

9. Online Support ( Team viewer/ Ammy Admin)

Description

Proposed Title :

Low Power and High Speed Area Efficient Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

Proposed System:

Low Power and Area Efficient

Software implementation:

TANNER

Existing System:

In the existing system to design the frequency multiplier with sequential pulse generator and generate the multiphase clocks using DLL core. Based on the sequential circuit, the pulse generator is generating the delay based clocks for the frequency multipliers. The previous design of the frequency multiplier is given below.

Disadvantages:

Low Speed with more delay

Proposed System:

The proposed DLL-based clock generator is composed of a DLL core and the proposed frequency multiplier, as shown in Fig. 2. To enhance the lock time, which is an important design parameter in the clock generator, a dual-edge-triggered phase-detector-based DLL core is adopted. Similar to previous frequency multipliers, the proposed frequency multiplier is also composed of a pulse generator, multiplication-ratio control logic, and an edge combiner.

To solve the speed and the reliability issues of previous edge combiners, an HSHR-EC, which consists of a precombining stage, overlap canceller, and push–pull stage, as shown in Fig. 3, is proposed. The two-step edge combiner, precombining, and push–pull stage are used to enhance the maximum multiplied clock frequency. The overlap canceller is used to guarantee the stable operation of the frequency multiplier.

Advantages:

Increases the speed and reduced the delay

Software implementation:

TANNER

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High Speed Low Power and Highly Reliable Frequency Multiplier for DLL Based Clock Generator

Description

Low Power and High Speed Area Efficient Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

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