Proposed Title :
Low Power High Speed Hybrid 1-bit Full Adder Circuit based 16-bit Vedic Multiplier Design
Improvement of this Project:
To Develop a 16 bit Vedic Multiplier design using the hybrid 1bit Full adder circuit.
- TANNER EDA
Today most of the processors require a very high-speed operation. Arithmetic operations such as addition, subtraction and multiplication are deployed in various digital circuits to speed up the process of computation. Multiplication is the most important arithmetic operation in signal processing applications. All the signal and data processing operations like digital signal processing involve multiplication. As speed is always a constraint in the multiplication operation, increase in speed can be achieved by reducing the number of steps in the computation process. In any digital system design, the three main performance parameters that determine the performance of the system are speed, power, and area.
Vedic mathematics is an ancient technique with the unique approach and it has got different rules in Sanskrit (Sutras meaning aphorisms. Vedic mathematics has been proved to be a robust technique for arithmetic operations. It has 16 rules that can be used for different arithmetic calculations. Vedic rules cover almost every branch of mathematics. They are also applicable to complex problems involving a large number of mathematical operations. The technique has been used in various domains including the design of low-power image compression and in signal processing domain. The application of a Vedic multiplier in encryption/decryption algorithm, Infinite Impulse Response (IIR) filters, and floating-point mathematics has been explored in the literature. These have been implemented using a field programmable gate array (FPGA). FPGA lies at the module level of design abstraction. These works show that using the concept of Vedic multiplication, the complexity of the multiplier can be reduced. Vedic multiplication of 2-bit and 4-bit Urdhva Tiryagbhyam Sutra is as illustrated in Figure.
As we go to the next level of design abstraction, i.e. the circuit level, an appropriate choice of logic design such as the classical complementary metal oxide semiconductor (CMOS), a transmission gate, or a novel gate diffusion input (GDI) can be explored to minimise the performance parameters. CMOS devices have high noise immunity and have low static power consumption but it requires a large area. Therefore, there is a need to look for an alternative that saves area.
In the work presented, a combination of Vedic multiplier and GDI logic is explored for the design of the 4-bit multiplier. Very less work has been reported in the literature for a combination of GDI and Vedic multiplication at the circuit level. The direct current (DC) analysis of the basic inverter is carried out to calculate the W/L ratios of transistors for different supply voltages. A GDI based inverter equivalent of a two-input NAND gate is compared with CMOS-based circuit. It is also analyzed using Monte Carlo simulations.
Morgenshtein et al. invented the GDI logic in 2002. To prove the practicability of GDI, an 8-bit carry look-ahead adder (CLA) was fabricated and tested which showed 45% reduction in the power-delay product than CMOS. Moaiyeri et al. demonstrated a GDI-based three-input XOR gate. It was found to be both area and power efficient. GDI eliminated the need for XOR/XNOR gates for designing a full adder cell. It provided an ultra-low power and high-speed, as reported in the work presented by Foroutan et al. CLA is the fastest multi-bit adder architecture being used in various high-speed processors, but it compromises on area and power due to its complex architecture when implemented using
The basic GDI cell consists of two transistors as shown in Fig. It has three inputs: G, P and N. The drain terminals of the two transistors are taken as output, while the source terminal of a p type metal oxide semiconductor (pMOS) act as one input and the source of the n-type metal oxide semiconductor (nMOS) act as another input. The bulk of nMOS and pMOS is connected to ground and supply voltage, respectively. the basic functions using a two-transistor (2T) GDI cell. GDI logic suffers from the issue of reduced signal swing at the output. To restore the output signal levels, buffers are required. Compares the number of transistors required for the implementation of various logic circuits using GDI (without buffer) and CMOS techniques. 4T at each output needs to be added to a buffer. Therefore, using GDI, any complex function can be designed with a less number of transistors as compared with the CMOS logic.
The basic difference in GDI and CMOS is seen in a two-input AND gate. The AND gate is 2 T in GDI, also, the AND gate followed by an inverter forms a NAND gate. Therefore, the NAND gate is 4T. For delay calculation, the logic effort of the circuit is estimated. The logical effort is the capacitance seen by the input of the NAND gate to that of an inverter. Assuming, the pMOS to nMOS sizing ratio to be 2:1. The capacitance seen by the input A is 3 and it is used to find logical effort. For the two-input CMOS NAND gate, the logical effort is 4, while for GDI it is 1. Therefore, GDI is believed to be an area efficient technique with reduced logical effort. The concept of both Vedic multiplication and GDI is independently efficient. Vedic multiplication helps in reduction of circuit delay while the GDI logic can be used to implement a circuit with less number of transistors. With less number of transistors, the switching node capacitance will be reduced as the logical effort reduces that shall, in turn, result in the reduction of dynamic power. Therefore, the GDI-based Vedic multiplier can be effective.
Tools and techniques
The prime objective of this work is to present an area and power efficient 4-bit Vedic multiplier. Circuit simulations are carried out in Tanner EDA tool for L = 130 nm. The predictive technology model (PTM)-based metal oxide semiconductor field effect transistor (MOSFET) parameters as L = 130 nm are tox = 1.6 nm, Vto = 0.284 V, Leff = 49 nm, Rdsw = 200 ohm, and Nch = 1.5 × 1018 cm −3. The efficiency of the circuit is determined in terms of delay, average power, and transistor count (TC). Pavg is given by the following equation: Pavg = Pstatic + Pdynamic 2 .
Pstatic, static power is contributed due to the dc currents flowing; these include the sub-threshold and parasitic p–n junction in conventional MOSFET when the circuit is at steady state. Pdynamic, dynamic power or switching power is the result of power dissipation in the circuit transition region from 0 → 1 or 1 → 0. Delay is defined in many ways. It is the time elapsed between the input and output crossing 0.5 × VDD . The TC is equivalent to the number of transistors in the circuit. It is an indicator of the total area of the circuit. The methodology for the design of a 4-bit Vedic multiplier is as follows:
- For a symmetric inverter design, the W/L ratio at various supply voltages is estimated.
- NAND gate is identified as the basic logic circuit that is differently implemented in GDI and CMOS logic. The DC characteristics of GDI logic NAND based inverter circuit is analyzed and compared in terms of noise margin (NM).
- Performance parameters of 2-bit GDI-based Vedic multiplier are compared with its CMOS counterpart.
- GDI logic based full adder, required for the design of a 4-bit Vedic multiplier is discussed.
- 4-bit GDI based Vedic multiplier is designed using: i. Basic logic gates like AND, half adder and full adder. It is named as ‘Implementation-1’. ii. 2-bit Vedic multiplier, which is named as ‘Implementation-2’.
- The performance of both implementations in terms of average power dissipation and TC is analyzed. 7. For both implementations, the effect of supply voltage variation on circuit performance parameter is also studied.
- The Conventional logic approach which exploited the features of different logic styles in order to reduces the overall performance.
- Consumes more power and efficiency is low.
On basis of Mathematical approach most of the DSP processor requires efficient and very high speed of operations. In that multiplication plays the major role, but it is lengthy and time consuming task. In many applications in electronics has proven the Vedic multiplier is very efficient and able to reducing the number of steps and circuit delay. Therefore, This paper proposes the new design technique of the multiplication using the concept of Vedic multiplier of urdhva Triyakbhyam sutra is implemented. The existing system of this paper proposes only 4 bit Vedic multiplier with conventional full adder design. Therefore, the efficient of conventional full adder is low and also it consumes more power and delay. Therefore, this paper proposes the 16 bit Vedic multiplier using the concept of urdhava triyakbhyam sutra and implemented this design using the low power and high speed hybrid full adder design. Thus, the proposed Vedic multiplier design using urdhava triyakbhyam sutra with high speed hybrid full adder design is high efficient and consumes less power, area and delay when compared to existing multiplier design using the conventional adder. Finally implemented the proposed 16 but Vedic multiplier design with the hybrid full adder in the TANNER Tool with 22nm PTM of CMOS Technology of power supply 1 Volt and analyzed its performance with area, power and delay.
2-bit Vedic multiplier
The block diagram of a 2-bit Vedic multiplier (or 2-bit Urdhva cell) is shown in Fig. 5. This has been simulated using CMOS as well as GDI. While the block diagram representation is the same for both the logic, the main difference is in the AND gate and XOR gate. The schematic of the XOR gate using GDI is shown in Fig. 6. The transient results of 2-bit Vedic multiplier using CMOS logic and GDI logic are shown in Fig. 7. The GDI-based circuit performs close to CMOS logic. The TC of GDI is 20 T (without buffer) as compared with 64 T in CMOS circuit. However, in the case of GDI, for restoring the voltage swing, total 16 T are added (considering buffer at each output), then the total number of transistors will become 36 T. The result of power dissipation and delay for variation of the supply voltage for GDI and CMOS is shown in Fig. 8a. The GDI-based circuit dissipates less power than the CMOS-based circuit. The power dissipation in both the circuits reduces the scaling of the supply voltage. At 1.2 V, CMOS-based circuits dissipate 5.742 μW average power and have 0.88 ns delay whereas the GDI-based circuit dissipates 2.295 μW and has 0.876 ns delay. Therefore, the GDI-based circuit dissipates ∼60% less average power and 43.75% fewer transistors than the CMOS logic for a similar transient response (delay characteristics).
GDI-based 4-bit Vedic multiplier
As discussed in Section 3.3, the GDI logic is efficient in terms of average power and TC. Therefore, the GDI-based 4-bit Vedic multiplier is analysed in this section. The 4-bit Vedic multiplier is designed by two methods, first is by using adders and logic gates and second is by using the basic 2-bit Vedic multiplier (2-bit Urdhva cell) as shown in Figs. 9a and b, respectively. The FPGA implementations of these architectures have already been found efficient in terms of delay and circuit complexity when compared with the conventional multipliers [6, 7]. The static power, dynamic power dissipation, and delay of both designs are compared and analysed. At the circuit level, GDI logic further helps in reduction of TC.
In both the block diagrams, 18 T GDI-based full adder is used. The transistor level circuit is shown in Fig. 10a. Fig. 10b shows its layout (without buffer). To estimate the robustness of the GDI logic based full adder, Monte Carlo simulations have been carried out as shown in Fig. 10c. The value of standard deviation of delay distribution for N = 1000 is 0.2701 ns. It shows that the circuit is immune to process variations.
For 4-bit Vedic multiplier, the total number of TCs including a buffer in implementation-1 is 178 T as compared with 242 T in implementation-2. The average power dissipation in implementation-1 is 13.0574 μW whereas it is 88.21 μW in implementation-2. Delay in both the designs is the same which is around 0.93 ns. These results are shown in Table 4. Therefore, implementation-1 is efficient in terms of average power dissipation and TC. We propose implementation-1 as a better circuit for the 4- bit Vedic multiplier. The layout for the proposed circuit is presented in Fig. 11. Fig. 8b shows the result of power dissipation and delay versus supply voltage for both implementations of the 4- bit Vedic multiplier. Implementation 1 dissipates less power than implementation 2. Therefore, the 4-bit Vedic multiplier based on half adders and full adders is better in terms of power dissipation and TC for almost a similar circuit delay.
- Vedic Multiplier reduces the complexity of the multiplier design.
- It is also applicable to complex problems involving a large number of mathematical
- the hybrid logic approach which exploited the features of different logic styles in order to improve the overall performance.
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Gate diffusion input based 4-bit Vedic multiplier design
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