Proposed Title :
Low Power High Speed Hybrid 1-bit Full Adder Circuit based 16-bit Vedic Multiplier Design
Improvement of this Project:
To Develop a 16 bit Vedic Multiplier design using the hybrid 1bit Full adder circuit.
- TANNER EDA
On basis of Mathematical approach most of the DSP processor requires efficient and very high speed of operations. In that multiplication plays the major role, but it is lengthy and time consuming task. In many applications in electronics has proven the Vedic multiplier is very efficient and able to reducing the number of steps and circuit delay. Therefore, This paper proposes the new design technique of the multiplication using the concept of Vedic multiplier of urdhva Triyakbhyam sutra is implemented. The existing system of this paper proposes only 4 bit Vedic multiplier with conventional full adder design. Therefore, the efficient of conventional full adder is low and also it consumes more power and delay. Therefore, this paper proposes the 16 bit Vedic multiplier using the concept of urdhava triyakbhyam sutra and implemented this design using the low power and high speed hybrid full adder design. Thus, the proposed Vedic multiplier design using urdhava triyakbhyam sutra with high speed hybrid full adder design is high efficient and consumes less power, area and delay when compared to existing multiplier design using the conventional adder. Finally implemented the proposed 16 but Vedic multiplier design with the hybrid full adder in the TANNER Tool with 22nm PTM of CMOS Technology of power supply 1 Volt and analyzed its performance with area, power and delay.
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Gate diffusion input based 4-bit Vedic multiplier design
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