## Description

**Existing System:**

EPILEPSY is a neurological condition characterized by the sudden and unforeseen occurrence of seizure, from which nearly 50 million people worldwide suffer, and 30% of the epilepsy patients have medically intractable seizure which is likely to lead to danger of accidents and even death of patients. However, if an early detection is made, 80% of the seizure activities can be treated effectively. The Electroencephalogram (EEG) signal is very effective for measuring the cranial nerve activity and has been used in human brain machine interfaces and neuron disease diagnosis. Currently one of the most common approaches for seizure evaluation using the EEG signal is to keep the patient in a hospital for long-term EEG, monitoring by physicians. However, this is extremely inconvenient, and there is no guarantee that there will be seizure event during the stay. In this case, automatic seizure detection and prediction systems would be valuable for these people, and successful detection may even leads to new approaches for seizure prevention. The machine learning approach is generally used in the realization of the automatic seizure detection or prediction systems. Many machine learning methods have been used, including extreme learning machine, na¨ıve Bayes, artificial neural network (ANN), support vector machine (SVM), etc. Among them, SVM, the state-of-art discriminative approaches, have recently attracted much attention, because of its high accuracy and adaptability to nonlinear decision boundaries.

The feature extraction (FE) of the EEG signal plays an important role in the classification accuracy of SVM. There are mainly four types of features used for characterizing the EEG signal: time domain (TD), frequency domain (FD), time-frequency domain (TFD), and nonlinear analysis (NA). TFD features capturing both frequency and time information are particularly effective for representing the nonstationary EEG signal, and can be extracted by the discrete wavelet transform (DWT), of which the subbands can be adapted to match physiological frequency bands of the EEG signal. The fourth order of Daubechies (db4) wavelet with the smoothing feature has been found appropriate for detecting changes of EEG signals. Therefore, adopting the db4 DWT to capture TFD information and match the physiological frequency bands of the EEG signal can achieve high accuracy.

There have been many software systems based on EEG and SVM for automatic seizure detection or prediction. For the convenience and portability, implementing the automatic seizure detection or prediction system in integrated circuits (ICs) is of great importance. However, for robust and accurate prediction, the moving window of the EEG signal is typically long and consequently massive hardware resource and energy are consumed, so the seizure detection system is more applicable to portable IC devices. Yoo et al. have implemented an on-chip linear SVM based seizure detector using the scalp EEG signal, and Altaf et al. later realized an on-chip nonlinear SVM based detector. These two systems used seven equal-bandwidth band-pass filters to extract the FD feature of the EEG signal.

However, none of the aforementioned automatic seizure detection IC systems carefully discussed integrating the training algorithm of SVM. Research results have shown that seizure patterns in EEG signals differ significantly between patients and between different ages of a patient, so the person-toperson and age-to-age variation in seizure patterns is a major challenge in the detection system for higher accuracy. Moreover, epilepsy seizure is sporadic. Hence, integrating the training algorithm on chip is very valuable for the portable detection system to be trained in time to adapt to the variations using the patient-specific and up-to-date EEG data.

However, training classical SVM is solving a quadratic programming (QP) problem which is computationally complex and energy-consuming, so integrating an efficient SVM training algorithm is very important. Suykens et al. proposed a least squares version of SVM (LSSVM) to transform solving the QP problem to a set of linear equations, which is less computationally complex and has good generalization performance. Huang et al. recently presented a parallel and scalable least-square solver to speed up training. As compared with classical SVM, the equality type constrains of LSSVM lead to much more support vectors, causing more multiply and add operations in detection phase. The seizure detection system is more frequently used in detection phase than learning and therefore the classical SVM is chosen.

Several classical SVM training algorithms such as chunking shrinking, digesting, Gilbert algorithm, and sequential minimal optimization (SMO) have been proposed. The Gilbert algorithm is slow on many problems when approaching the final solution. To solve the inefficiency, Martin et al. later proposed the modified Gilbert algorithm which has been accelerated on FPGAs by Papadonikolakis et al. and Rabieah et al. by computing kernels in parallel using scalable hypertiles and processing elements, respectively. The SMO algorithm which reduces the chunk size to two makes learning feasible for problems with large number of training samples and limited hardware resource, and has been implemented in hardware. However, the SMO algorithm has two inefficiencies. First, it checks the optimality of the remaining samples based on the assumption that the current two optimized samples satisfy the optimality. Thus it may identify samples satisfying the optimality as violating ones, and vice versa, which leads to additional iterations. Second, its heuristic selection method results in complex controller in hardware implementation.

Keerthi et al. uses the boundaries of the sample subsets to select the samples to be optimized in the modified SMO (MSMO) algorithm, which surpasses the heuristic selection method of the SMO algorithm. The boundaries are also used to check the optimality of the samples, which avoids the optimality-satisfaction assumption in the SMO algorithm and consequently requires fewer iterations and performs more efficiently on all the benchmark datasets. Since we aim at developing a portable seizure detection system with on-chip training capability, where the energy-efficiency is a major concern, the MSMO algorithm is a better choice to be integrated.

According to the above discussion, this paper proposes a VLSI design of nonlinear SVM-based seizure detection system, which integrates the MSMO algorithm and the db4 DWT for achieving efficient on-chip training capability and high detection accuracy. The proposed design is verified on an FPGA device and tested using two publicly available datasets.

**Disadvantages:**

- Not having more Accuracy Prediction
- More logic size and delay
- More memory size in SVM method

**Proposed System:**

In this recent research of automatic seizure detection system is very convenient to monitor epilepsy patients in anywhere at the time of predictions previously and alert hospitals and related persons. In this work where design a high efficiency and attain high detection accuracy system of seizure detection in system on chip, this paper present with non linear support vector machine (SVM) with classifications method and also consists of seizure prediction feature extraction method. In the feature extraction method discrete wavelet transform will level Daubechies to fit the physiological bands of electroencephalogram (EEG) signals. In this existing system of SVM with modified sequential minimal optimization in Gaussian Kernel algorithm to perform efficient on chip learning, but it will take more logic size due to cause of more number of multipliers. Here, this proposed work presents this SVM with Gaussian Kernel algorithm design in Truncated method using Signed-Unsigned Truncation multiplier, it will reduced the area size in internal and external, thus its having n size outputs from n x n inputs, this experimental results will shown in VLSI System of XILINX FPGA XC6SLX100T-2CSG484, with proved in the terms of Area, delay and power.

Fig. 1 shows the architecture of the proposed SVM-based seizure detection system, which consists of a DDR2 SDRAM Controller (DSC) module, an FE module, and an SVM module. The massive raw EEG data is stored in an off-chip SDRAM. The DSC module is an IP-based industry-standard module which controls the communication between the system and the SDRAM. First, the raw EEG data are processed by FE module. The three-level db4 DWT decomposes the EEG signal into four sub bands. The mean absolute values (mav) and variances (var) of the DWT coefficients in each of the four sub bands are then calculated in the following sub modules MAV and VAR, respectively, to produce the 8-dimensional feature vector. Then the 8-dimensional feature vector is sent to SVM module, which has the learning and detecting functions. In the learning phase, the hyper-plane of the SVM classifier with the seizure-onset side against the seizure-free side is learned using training samples. In the detecting phase, the trained SVM detects and labels the seizure onset. The signal Mode determines which phase SVM module works in. The fixed-point arithmetic is used in the system. The two datasets used to verify the designed system was digitized into 10 bits and 16 bits, respectively. For reducing the distortion caused by transforming the floating-point format into the fixed-point format, the desired finite word length is analyzed through software simulation and a 3.12 signed fixed point format with 1 sign bit, 3 integer bits, and 12 decimal bits is determined.

The architecture of SVM module is shown in Fig. 5. It consists of four function submodules, Exam submodule (Exam), Lagrange Multiplier Updating submodule (LMU), Fi and Boundaries Updating submodule (FBU), and Gaussian Kernel submodule (GK), and an MSMO controller submodule (SMOC). In addition, Cache is used by FBU for caching F is and K(Xi, X j )s. Memory is used for storing X is, y is, and αi s. The three steps of the MSMO algorithm are mapped on Exam, LMU, and FBU, respectively, which are controlled by SMOC. The interrupt mechanism is used in SMOC to accelerate the convergence of the algorithm in the VLSI architecture. On-chip Cache can further improve the efficiency by reducing the recalculation of K(Xi, Xj ) for updating the prediction errors F is. Exam submodule selects αi2 which violates the KKT condition (9) to be optimized and determines the corresponding αi1 according to (10), executing Step 1 in Table I. LMU updates αi1 and αi2 according to (11)–(13), executing Step 2 in Table I. FBU updates Fi : i ∈ I0 ∪ {i1 , i2 }, bup , blow , iup , and ilow , executing Step 3 in Table I. GK calculates K(Xi, Xj ) according to (8), which is used by LMU and FBU.

**FIR Filter Design using Truncation Multiplier in DWT:**

In the Finite Impulse response(FIR) is widely used in several digital signal processing application, will have highly compactable with high performance and low power in gadgets application, such as audio and video signal processing, software define radio, telecommunication and so on. In this FIR filter is very often and need to support in digital signal processing to high sampling rate, impulse response based filtering order and cut-off frequency. In this FIR filter design, will have number of adders, multipliers and delayed element required to response filter output. An FIR filter it not required a feedback based inputs, which means, this filters is not computed any rounding errors in summing and multiplication. An FIR filter is inherently stable to produce output values and it can be no maximum value impulse response Nth order times, it can easily design and also easily configure sequence of linear phase coefficient, it will also applicable to detect the phase sensitive applications such as crossover filter design, mastering, seismology and data communications. In this filter to meet the coefficient specification in certain things, which can be suitable with time domain and frequency domain. The main disadvantages of FIR filter design are more power consumption and large area size is required for multipliers, adders and delayed element in number of Nth order based TAP. In the High performance FIR Filter architecture will have MCM multiplication and normal adders will perform inherently pipelined and also produced the results on significant way with save computation results. In the FIR filter design will take large area and also take the stringent order to meet frequency range with high performance. The main priority of this FIR filter design is Multiplier, adders and delayed elements, the architecture of Fig.3 will have to used MCM (Multiplier constant Multiplication) and Normal adders in this architecture design, it will take more area and more power consumption, and also low performance to detect sign and unsigned operation of multiplication and addition with carry operation.

In this architecture of Fig.1, it notified the FIR Filter will contain number of TAP (multiplier, delay, adder), the area and power of this FIR filter will take this multiplier and adder only. In the normal or MCM multiplier will provided the 16bit output for 8bit input, these output isprovided to adder, So the adder design it will take 16bit addition. Here X(n) is the input and Y(n) is the output of this filter design, H(0), H(1), H(2) … H(n) is the coefficient of this filter design, this coefficient will take from MATLAB with the help of FDA (Filter design analysis) Tool, and also possible to fix the operations such as low pass filter design, band pass filter design, high pass filter design, band stop filter design, and also fix the operation range of cut off frequency, sampling frequency and so on.

In the architecture of Fig.4, the multiplier and adders will have designed for Truncated Multiplier. In this method of truncated architecture is fully designed based on full adders, here carry operation is followed as per the same operation of sum, based upon this architecture it will take more critical path delay, propagation delay, and its perform slowest operation of arithmetic functions. A goal of this truncated multiplier is to reduce the large area in the internal and external architecture using rounded based technique, which computed the truncation multiplier will have summing the two n-bit partial products, this operation of two n-bits, the MSB of most significant rows and columns with truncated, deleted and rounding to correction in variable method. A normal multiplier of n x n bit computes and get the weighted sum of output of 2n bits. A multiplier in signal processing the output represented the MSB part of n bits is useful, because it’s signed oriented outputs, example of this design such as digital signal based application.

A truncated multiplier is a hardware efficient multiplier, it will useful to increases the tradeoff accuracy and reduced the hardware cost, since this truncated multiplier will help to produce the output of n-bits form n x n bits of multiplication, it will take less significant, and some of the partial products are removed and also replace using the technique of deletion, reduction and truncation. In the partial products of this multiplier more number of columns are eliminated regarding the area and power consumption, in case the delay also decreases with compare to the normal operation of 2n outputs of n x n multiplier, but some drawbacks will have on this truncated multiplication, because this multiplier is not concentrated on carry operation, such as carry addition and carry skip operation, here used number of full adders for addition, but not implemented the simple and efficient gate level implementation with carry operation to significantly reduced the area, power and delay.

**Advantages:**

- Having more Accuracy Prediction
- Less logic size and delay
- Less memory size in SVM method

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