FPGA Implementation of 2D FFT Implementation using radix-4 design architecture with Reversible Array Multiplier

• To build the SEU Tolerant 2D-FFT utilizing radix-4 design architecture instead of radix-2 to minimize the number of iterations in 2D-FFT.
• To design SEU Tolerant 2D-FFT using Reversible Array Multiplier to reduce the logic size with garbage signals.
• Compared the proposed architecture with Conventional Array Multiplier and proved the performance of area, delay and power in Xilinx Vivado Artix-7 FPGA.

• Modelsim
• Xilinx Vivado

Proposed System:

The two-dimensional fast Fourier transform (FFT) has been widely employed in the processing of radar signals. Field programmable gate array (FPGA) is an excellent hardware solution for this application due to the necessity for high performance. Single-event upsets (SEUs) in static random access memory (SRAM)-based FPGAs can produce a large number of soft errors in space-borne radar platforms such as synthetic aperture radar (SAR). In this regard, safeguarding the 2D-FFT implemented in FPGA against SEUs is critical. In this paper, we examine the significant weakness caused by SEUs in the 2D-FFT process and then provide a 2D-FFT design with strong SEU resilience. The design takes advantage of many anti-SEU techniques. Partially triple modular redundancy (TMR) is utilized in FFT for butterfly control. When reading and writing data buffers, error correcting code (ECC) is used. Furthermore, critical control registers use secure finite state machines (FSM). The findings of fault injection reveal that all of these reinforcement approaches help to improve the capacity to attenuate SEU impacts. Instead of radix-2, the proposed architecture builds the SEU Tolerant 2D-FFT utilizing radix-4 design architecture to minimize the number of iterations in 2D-FFT. To minimize the logic size with garbage signals, SEU Tolerant 2D-FFT was designed utilizing Reversible Array Multiplier. The proposed structure was compared to the conventional Array multiplier and the performance of area, latency, and power in the Xilinx Vivado Aritix-7 FPGA was demonstrated.

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Design of SEU Tolerant 2D-FFT in SRAM-based FPGA