Proposed Title :
FPGA Implementation of Truncated Sparse FIR Filter with Reduced Effective Length
Improvement of this Project:
To Design a Sparse 32-TAP Band Pass FIR Filter at 100 MHz sampling frequency, 5 to 10MHz Cut Off frequency.
To Modified the MCM Multiplier instead of Truncated Multiplier to reduced the area, delay and power.
Linear phase finite impulse response (FIR) filters enjoy many attractive properties such as exact linear phase, guaranteed stability and low coefficient sensitivity [. They are widely employed in various digital signal processing (DSP) applications. However, the implementation cost and power consumption of FIR filters are usually higher than their infinite impulse response (IIR) counterparts. Therefore, it is crucial to reduce the computational complexity of FIR filters for area and power efficient DSP system design. It is well known that multipliers are expensive in terms of area and power consumption. Since the multipliers and the structural adders corresponding to the zero coefficients are not required, the implementation cost and power consumption of FIR filters can therefore be lowered by reducing the number of non-zero filter coefficients. These filters with many zero coefficients are called sparse FIR filters.
The sparse FIR filter design problem has been intensively studied in the past decades. Intuitively, the sparsity of a filter can be evaluated by the l0-norm of the filter coefficient vector. However, the l0-norm minimization problem is nonconvex, making it difficult to find a global optimal solution . The- oretically, exhaustive search can be used to search for sparse solutions without sacrificing the optimality. But due to the huge search space, the computational complexity of exhaustive search can be extremely high, especially for high-order filters. More sophisticated search methods can be used to intelligently search all the possible sparse solutions., a depth-first branch-and-bound algorithm is proposed to gradually locate the zero coefficients and traverse all the possible solutions to search for global optimal designs. But its non-polynomial complexity makes it computationally intensive for high-order filter design as well. Alternatively, the sparse FIR filter design problem can be approximated to a l1-norm minimization problem, which is convex, with some relaxation techniques. Sparsity is achieved by minimizing the approximation error through l1-norm minimization. A more sophisticated iterative l1-norm optimization algorithm is presented. In this algorithm, a weighting function which is updated in each iteration is introduced to assign larger weights to the small valued coefficients and vice versa. As such, more potential positions of the zero coefficients will be gradually located with larger weights.
More l1-norm minimization based algorithms have been proposed. Generally, all these methods contain two stages. In the first stage, various strategies with specific objec- tives are employed to locate the potential positions of zero coefficients. While in the second stage, some of these positions are assigned to zero and the others are further optimized for the minimization of approximation errors. However, these algorithms are inevitable to result in additional approximation errors under slack conditions. Two heuristic algorithms are proposed to design sparse FIR filters based on linear programming. These two algorithms gradually propel the non-zero filter coefficients to zeros until the given approximation error constraints are violated. The first algorithm nullifies the non-zero coefficient which results in the minimum increase of the approximation error, while the second one transforms the coefficient with the smallest magnitude in each iteration.
- High area occupied.
- High power Consumption.
- Does not support Bit Inter-leaving.
- Less sparisty
- More iteration
- ore approximation error
In a recent technology of Digital domain a filter is a major priority one in all gadgets with digital signal processing applications. These Digital FIR Filter will provide more efficiency while using more number of TAP, such us multiplier, adder, delay and its obtain more effective length, thus it will take mini-max approximation error. This proposed work will introduced a l0-norm minimization in FIR filter with liner phase method regarding to reduce sparse complexity and reduce mini-max approximation error for sparsity maximization. Here, this Sparse FIR Filter will designed using Truncated Multiplier to reduced number of full adder in Sparse FIR and this Truncated Multiplier will give n output bits from n x n multiplications, therefore it will reduced number of addition bits in Sparse FIR filer operations. This proposed method will designed in 32-TAP Band pass level at 100 MHz Sampling Frequency with 5 to 10MHz Cut Off frequency. Finally this work will designed in VHDL, and simulated in Modelsim, and synthesized in Xilinx FPGA, and compared all the parameters in terms of area, delay and power.
- More sparsity
- Less Iteration
- Less Approximation error
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Design of Sparse FIR Filters With Reduced Effective Length
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