Proposed Title :
CMOS 45nm Implementation of Non-Destructive Column Selection Enabled 10T SRAM with Diff-VDD Write and Dropped-VDD Read for Power and Area Reduction
Improvement of this Project:
To design a 8-Bit non-destructive column selection SE 10T SRAM in 45 CMOS Technology and compared with existing 65nm CMOS Technology
- TANNER EDA
In Memory system, SRAM plays major role in storing bit .but for low voltage applicaton SRAM gives loss in both area and power. And they suffered from Bit Interleaving (column selection).In this proposed SE -10T SRAM is designed for supporting Bit Interleaving and also for power reduction. In addition featuring bit line-shared data-aware write assist to enable the column-selection structure . Further here 8 bit 10T SRAM also designed and implemented. Compare to the existing method, the proposed design have more power reduction and area size. Finally, the proposed design is implemented in the TANNER EDA at 45nm CMOS Technology with 0.9V input voltage and proved the comparison in terms of area power and delay.
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Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction
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