The ultralow-voltage operation of digital circuits offers a niche for applications with high constraints on energy efficiency or low power consumption, such as implantable instruments, biomedical devices, and wireless sensors. Compared with other circuits, SRAM has always drawn much more attention in low-voltage regions since it places a restriction on VDD scaling and dominates the major power and performance of the chips
Traditional 6T SRAM widely used in commercial ICs has been a workhorse for many years. While providing beneficial concerning area efficiency, it is associated with the challenge of read stability and write ability in low-voltage domains toward process, voltage, and temperature variations, thus resulting in the degraded circuit behavior or ever failure. The major reason for the VDD-min limitation in 6T SRAM is the contradiction between read and write requirements as well as the direct-read-access mechanism .
other variations further developed from the source-follower filter for high frequency applications can also be found .
To realize the low-voltage operation, a superior alternative is the single-ended 8T (SE-8T) SRAM cell . It separates the read path from the cell core by adding an isolated 2T read port, enabling read and write VDD-mins to be capable of optimizing independently. Of course, several other typical SRAM cells are also proposed for low-voltage applications. However, most of these new SRAM cells, including the SE-8T cell, suffer from the half-select disturbance. In other words, they are not able to support the bit-interleaving (as well as called column selection) architecture which is extensively utilized in SRAMs to afford soft error immunity in combining with the error correction code . Therefore, some bit-interleaving enabled SRAM cells are preferred to be adopted in the SRAM design. The representative one is the differential 10T (Diff-10T) bit cell . It uses row-wise and column-line assists to form the cross-point configuration to eradicate the half-select problem together with the read destruction. Nevertheless, this bit cell circuit has more transistors, introducing remarkable area overhead. To make the matter worse, its write performance and write noise margin (WNM) are seriously exacerbated by the existence of the series-connected write access mechanism. Although the area cost is completely acceptable in advanced ultra deep- submicrometer regions, the poor write ability imparts a limitation on VDD-min.
- High area occupied.
- High power Consumption.
- Does not support Bit Inter-leaving.
In Memory system, SRAM plays major role in storing bit .but for low voltage applicaton SRAM gives loss in both area and power. And they suffered from Bit Interleaving (column selection).In this proposed SE -10T SRAM is designed for supporting Bit Interleaving and also for power reduction. In addition featuring bit line-shared data-aware write assist to enable the column-selection structure . Further here 8 bit 10T SRAM also designed and implemented. Compare to the existing method, the proposed design have more power reduction and area size. Finally, the proposed design is implemented in the TANNER EDA at 45nm CMOS Technology with 0.9V input voltage and proved the comparison in terms of area power and delay.
The original SE-10T SRAM cell of the proposed bit cell is shown in Fig. 1. A 4T read port composed of an inverter and a transmission gate (TG) is added to the 6T cell, isolating the read path from internal storage nodes. The inverter (M6 and M7) is driven by node QB and drives the read bit-line (RBL) through TG (M8 and M9) which is controlled by two complementary read word lines (WLs). This SE-10T cell can fully charge or discharge RBL by itself during a read operation. Thus, it is totally unnecessary to prepare a pre-charge circuit for RBL. The dynamic power is consumed on RBL just when the read datum is changed. That is to say, the dynamic power dissipation on RBL is zero if consecutive “0”s or consecutive “1”s are read out. This feature makes it suitable for video processing since image data have the special correlation, and similar data are read out in consecutive cycles . Unfortunately, due to its 6T-like write operation, when initiating a write in a column-selection array, unselected cells in a row (or called half-selected cells) on the selected WL perform dummy read which indicates that the cells just undergo a read behavior rather than readout during a write operation, thereby experiencing the storage node upset similar to read disturb in the 6T cell. In other words, it is not eligible for the bit-interleaving architecture. In addition, the full rail-to-rail swing occurred on RBL congenitally dissipates more power compared with the differential readout. Meanwhile, bitlines incur more leakage current because of TG.
This SE-10T cell has been presented in . However, our proposed 10T (thereafter called P-10T) circuit topology is different from the earlier design. Fig. 2 shows the P-10T based on the SE-10T cell. It exhibits improvements in the following aspects compared with the previous circuit.
First of all, the bitline-shared data-aware scheme is adopted to enable the column-selection architecture. In Fig. 2, the 6T part of the SE-10T cell is motivated by the y-direction (column direction) WL [column WL (CWL)]. In addition, two additional access transistors (M10 and M11) are added to connect the 6T cell, which are activated by the x-direction (row direction) write WL (WWL) and at the same time are powered by a complementary write bit line pair (WBL and WBLB). Every extra access transistor and write bit line are shared by two adjacent 10T cells in a row. During a write operation, the data are written into the storage core from shared write bit lines via shared access transistors and internal access transistors, just when row WL and column WL are all switched ON. The proposed bit-interleaving-enabled scheme is different from the previous design in  where the SRAM array is also able to be column-interleaved by vertical and horizontal WLs. Nonetheless, its write access devices are shared by several bit cells in a column, whereas the write access ones are shared by two bit cells in a row in our design.
Second, a Diff-VDD strategy is utilized to ameliorate the cell’s write ability. We can observe from Fig. 2 that the power supplies of the 6T cell are coupled to two different virtual power lines (VDDM1 and
Excluding the body effect, the gm-C equivalent circuit in Fig. 1(c) can represent the small-signal operation of both Nand P-input cells. Using the circuit in Fig. 1(c) as a filter prototype, by straightforward analysis, we have VDDM2) produced by the Diff-VDD generator. Therein, VDDM1 is generated by ANDing CWL and WBLB to drive a power-ON inverter, in which the source terminals of pMOS and nMOS are all connected to VDD. Similarly, VDDM2 is obtained by ANDing CWL and WBL to drive the other power-ON inverter. These two VDDM lines are dropped differentially according to the values of the required written data. VDDM1 line is dropped at a write access for a “0” datum on WBL (WBLB = 1), while VDDM2 line is inversely dropped for a “1” write access.
Finally, we employ a dropped-VDD biasing for the read port, resulting in utterly noticeable power reduction. As shown in Fig. 2, the power supply of the 4T read port is biased over a virtual power line VDDM3 which is produced through several diode-connected nMOSs. In general, a voltage drop (equal to Vthn approximately) is established across these diode-connected nMOSs, making RBL swing decline to VDD −|Vthn|. Consequently, much power saving is attained for a read operation. Normally, the values of the VDDM1, VDDM2, and VDDM3 all equal to approximately 0.75 V at VDD = 1.0 V in this design in a 65-nm CMOS, while the value of 0.39 V is obtained at VDD = 0.5 V. Admittedly, the power drivers of these three virtual power lines also introduce area overhead. It is estimated that less than 5% area contribution to the total array area is achieved for the drivers.
Fig. 3 shows the cell layout view and the arrangement of WLs, bit lines, and power lines. Since the row-access devices are shared by two adjacent SE-10T cells, the average area per P-10T is just increased by 8% compared with SE-10T. To relax the routing congestion, WLs except the CWL traverse the cell with M3 while other signals run vertical on M2. Besides, global power rails are inserted between two signals or virtual power rails on purpose, and long signal wires in parallel are avoided, mitigating the influence from the crosstalk noise.
The property comparisons of several typical bit cells are tabulated in Table I. For the SE-8T cell, it exhibits ample read stability and write ability without compromising much area overhead, but the bit inter leaving architecture is disabled owing to its 6T-like write mode. The SE-10T cell has the same properties as that of the SE-8T cell except the non-pre-charge circuit and the inferiority of the area. As far as the Diff-10T cell is concerned, it addresses the problems of the read disturb and half-selection but with the write ability and area sacrificed. Comparatively, the P-10T cell acquires these features only at the cost of the extra area.
- Low Area .
- Low power Consumption.
- Support Bit Inter-leaving.