Lower Power and Area Efficient FIR Filter design using Optimized Conventional Shift & Add Multiplier Design
Improvement of this project :
Implement 8×8 Shift & Add Multiplier design with Signed and Unsigned configuration.
Implement Signed Shift & Add Multiplier design in 8th Order FIR Filter design, and proved the performance of area, delay and power.
FPGAs are adept at developing and implementing DSP systems ranging from basic to intricate. The performance of the FPGA-based design may be significantly influenced by several aspects, such as the choice of an FPGA board, the Electronic Design Automation Tool, and the Programming Techniques used to enhance the efficiency of the algorithm. The algorithm optimization yields a more condensed design in terms of both area and attained frequency. The primary constraint in optimizing DSP algorithms is in the complexity of the multiplier, which is particularly noticeable in algorithms such as FIR, IIR, FFT, and others. Here, the hardware complexity of designing a FIR Filter for simple digital signal processing application is decreased by using an improved traditional shift and Add Multiplier design. Despite using many optimization techniques for hardware implementation, the power consumption in FIR Filter design remains a challenge. This study also examined the design of signed and unsigned shift and Add Multiplier, with the signed multiplier specifically designed with FIR Filter design. The FIR Filter design utilizes the Xilinx Vertex-5 FPGA in conjunction with ISE 14.2 simulators. The parameters to be compared include the Lookup tables (which are the Logic elements of FPGA), adder/subtractors, and multiplexers. Additionally, performance characteristics such as operating frequency, latency, and total levels of logic (representing the route traveled by the signal in register transfer level) will also be considered. The results indicate that the proposed design is a very favorable alternative to the traditional shift and add method.
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An Optimization in Conventional Shift &Add Multiplier for Area-Efficient Implementation on FPGA
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