FPGA Implementation of Approximate Wallace Tree Multiplier design using Approximate full adder based 4:2 compressor
Improvement of this project :
To design the Approximate 8×8 Wallace Tree Multiplier using Approximate Full adder and Half Adder
To design the 4:2 Compressor using Approximate Full Adder design
To design the Approximate 8×8 Wallace Tree Multiplier using Approximate Compressor design
High performance Ladner Fischer Parallel prefix adder used for final additions.
In any digital gadgets application based arithmetic operations a multiplier will take major role to support several multiplication algorithms, by the way it’s taken more logic size and power consumptions. As per the research of last few decades among various multiplication algorithm, a Wallace tree multiplication will provide effective terms of low logic sizes and more speed of operations. In a recent arithmetic applications based circuit design will have more demand with high speed and low area, in this manner the proposed approach of this work will improve the speed of Wallace tree multiplier using approximate 4:2 compressors, approximate full adder and approximate half adder method. Thus, the proposed method will take less logic size and power consumptions compare to traditional Wallace tree multiplier. Similarly, the proposed multiplication will have designed using Verilog HDL, and Synthesis in Xilinx Vertex-5 FPGA, and hence proved all the parameters in terms of number of LUT, slice registers, IOB, delay and power.
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Design and Implementation of an 8-bit Approximate Wallace Tree Multiplier for Energy Efficient Deep Neural Networks
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